[kayson]

Circuit designer here - feel free to ask any questions about the manufacturing process, design etc.

Having a thorough understanding of the process, I thought this was hilarious. But if you really want to understand the process, it's pretty terrible. It spends 10 steps on making a wafer, and then the bulk of the actual process is condensed to 16.

[gautamcgoel]

Suppose I want to make a custom ASIC with 20B transistors. I have a lot of money to spend but no semiconductor experience. How do I go about hiring good chip designers? How much $ should I realistically expect to spend on design, verification, and fabrication, respectively? I've heard $20M is the ballpark for a mask on a leading edge node. What is the marginal cost per CPU?

[kayson]

That sounds way too high for mask costs. You're definitely looking at 7 figures, but I don't think they've yet hit 8. Unfortunately the answer to all of your budget questions is: it depends. It's going to scale with the complexity of your requirements. Something like a custom ARM chip with heavily custom machine learning and signal processing, high speed clocking, etc, would probably need a decent sized team and a few years. On the other hand, there are tiny teams in Asia that crank out bitcoin mining ASICs like candy.

I'm going to guess at a number and say you're probably looking at $10-20MM all in.

As far as hiring good designers, you really need the relevant technical background to screen them. Assuming you need a team, I would suggest starting with someone in a director position at a large company with experience in your area of interest. They would be able to more concretely define the project and determine human resource requirements/allocation.

If your ASIC is just large but not complex (meaning lots of repeated structures), and you can get away with just a few strong designers, I would suggest hiring a consultant to help you define the project and screen candidates. EE profs at your local university might be a good start.

Feel free to shoot me an email (in my profile) if you want to describe your project in more depth and I'd be happy to offer what advice I can.

[nwiswell]

> That sounds way too high for mask costs. You're definitely looking at 7 figures, but I don't think they've yet hit 8.

7nm logic mask set costs are estimated at $10.5M. Of course you could always use a slightly less leading-edge node and save a lot of money.

Slide 13:

https://semiwiki.com/wp-content/uploads/2020/03/Lithovision-...

[kayson]

Huh you might be right, if only just. It says it's an estimate, but that probably means 3nm nodes will be >$10MM for sure

[foobiekr]

20B is slightly bigger than the Apple M! (10nm) and slightly smaller than the 32 core Epyc (14nm), which you should consider are both very substantial projects from a headcount, simulation, tools, licensing, etc.

To put it in perspective, a company a friend founded that is doing a very large but very regular ASIC for TSMC 10nm raised twice what you're ballparking and will end up doing another raise before tapeout. Chips nowadays are _expensive_ if you're anywhere near state of the art. The people who do very high performance chips are also very expensive.

But I'm also guessing that unless you're doing a bitcoin hashing chip, AI chip, or GPU, all of which is regular, your scale estimate is probably very off. If you're doing any of those, just don't.

That said, there are SOC vendors who do core plus, so it's possible that if this is just an accelerator, no matter how wide, you might be able to outsource the whole thing.

[7373737373]

Do you think chips in the 10k-100k transistor range will some day be able to be produced by hobbyists? Or are the chemicals simply too dangerous and machines too expensive to be affordable at that scale?

[kayson]

No, I don't think so. But it's not because of the chemicals or machines. There's not really any demand for it. Most hobbyist "ICs" are fully digital and can already be realized on an FPGA. For simpler applications, you can probably program a microcontroller to do what you want.

Integrated circuits are appealing to industry because they're integrated - they can be smaller and they reduce cost (long term; still need the upfront investment). These are important things for many products, especially in RF, but they aren't really driving factors for hobbyists.

That being said, people are trying! http://sam.zeloof.xyz/second-ic/

[zsmi]

I think it probably depends on what "produced" means here.

If it means designs inside an EDA environment, design get submitted and shows up realized, then that is possible now. And it's not all that expensive. eFabless chip ignite is quoting ~$10K for 100 QFNs in 130nm. That's getting into beater car territory. https://efabless.com/chipignite/2110C

If it means actually fabricate then I think there is no way because a DIY won't have the scale to compete on price and they won't be able to bring any custom processing step to justify being at boutique scale. Think about PCBs. We used to make them ourselves with chemical etch. Now I don't even use breadboards because a custom bare fab is $5 and the components cost more than that. I also get a much better electrical result, and it doesn't fall apart if I look at it funny.

The main problem with ASICs is the amount of skill/time that it takes to do it right. Floor planning, track planning, closing timing, etc. etc. on an ASIC is much harder than an FPGA. You don't even have to do half those things on an FPGA.

With an FPGA one can almost get compile and go if you're willing to be loose on area and performance. ASIC CAD tooling is no where near that at the moment. Closed or open source.

[7373737373]

Yeah, I saw and am amazed by his work, which made me wonder whether chip manufacturing could get as streamlined, compact and mainstream as 3d printing is today!

[kayson]

I think the first step is making EDA (electronic design automation) more accessible. Right now, even if you could do the fabrication yourself, doing a real, useful design would be just as challenging because the tools are all proprietary and expensive.

[guerrilla]

What about someone buying old machines and providing it as a service like the low-end PCB manufacturers today? They seem to be doing okay.

[R0b0t1]

It's possible. The chemicals are not too dangerous, and yes, you can train yourself. Maybe it wouldn't fly in the EU.

[afr0ck]

> Maybe it wouldn't fly in the EU.

May I ask why?

[R0b0t1]

Because Europeans are afraid of everything. I was trying to avoid a comment that seemed politically charged but I don't know any other way to say it.

I was into hobby chemistry for a while -- people trying to do anything in the EU find it almost impossible. Poland and Eastern Europe are better about it, but eh.

[wrycoder]

Even in the US, chemistry is avoided and even deplored. Where are the Christmas chemistry sets of yore? People are scared to death by anything having to do with “chemistry”, yet they think nothing of jumping into brewing.

[YetAnotherNick]

Being scared and being banned are two separate things. If you want to see how many dangerous chemicals are available online in US see Cody's lab or NileRed.

[ic_dummy]

How are the pn junctions created? The article says I can "optionally" dope the wafers. Why is that optional? Are they doped to create both p and n areas, or just one type? Or are multiple wafers used? Or are areas somehow doped after etching? Thank you for entertaining my dumb software person questions.

[kayson]

This is one area the article did a very poor job of explaining. In some processes, you treat the entire wafer before you get started with the rest of the procedure. One example that does this is SOI (silicon on insulator) processes. Others may not need this "global" doping, and from what I know most bulk silicon cmos processes do not do this.

Then you do the lithography (photoresist developing, etching, etc) to expose specific regions on the silicon that you want to dope to create devices like transistors, for example. So first you might expose all of the p-type transistor (PMOS) diffusion areas and dope them. Then you'd remove all the photoresist, repeat the procedure to expose n-type diffusions and dope that. And so on for the various needs of that particular wafer.

PN junctions are created simply by having p-type doped silicon adjacent to n-type doped silicon. The boundary between the two is the PN junction. In practice what I usually see is a square of one type with a ring around it of the other, but these devices are not frequently used.

[GhettoComputers]

Can you talk about if the US has microchip supremacy due to raw materials from Spuce Pine's pure silicon, and if there are any sources that are almost as good or being used instead? Is it almost like De Beer's diamond monopoly?

Do you use any countries or specific factories that do better refinement or are the raw materials directly shipped to the manufacturing country? What do you make from the wafers usually? Are certain sizes much harder to make? I know for example that larger sensor for digital cameras are much harder to make. I also heard of redundant circuits used to increase the yields of chips, how often is this used and when is it most useful versus less?

[kayson]

The US may have technological supremacy when it comes to design and the resultant products, but it lags behind in terms of actually manufacturing semiconductors. The dominant players are in Asia (TSMC, Samsung, GF) and Europe (GF). Intel has their own fabs, but they are currently behind the competition, and up until very recently only fabricated their own products. There are a lot of other companies in the industry with fabs, but they're generally making their own products - discrete devices - rather than integrated circuits/System-on-a-Chip's.

Another issue is the equipment used for manufacturing. It's very hard to come by, and the classic example is ASML (Netherlands), which dominates the market for lithography equipment.

I work on the design side, not in a fab, so I can't tell you much about sourcing or refining the silicon for wafers. Wafers are used to make every single microchip you can imagine. There has been a slow but continuous push towards using larger wafers, since its more cost-effective. I imagine it's more difficult, but couldn't tell you any specifics.

As far as manufacturing each individual integrated circuit: yes, larger is harder to manufacture because there is more physical space for a defect to occur. There are some design challenges as well when you get very large, but it's not a significant overhead because you're usually doing your design in sub-pieces anyways.

Some designs do use redundancy, as you mentioned. This is more often the case for very large, very uniform structures, like DRAM, flash, CPU cache, etc. But there's a tradeoff because you waste money on that redundancy for every chip that comes out with no defects. And there's overhead to actually testing the part in order to utilize the redundancy. In my experience, yields are targeted at the high 90%s these days, so the redundancy would have to be very cheap to be worth it. For almost all RF, analog, and mixed-signal circuits, there is no redundancy. I'd say most digital circuits, except the largest, also don't have any.

[GhettoComputers]

Thank you so much for this industry info. When you design, do you think that Shenzhen is the best in terms of innovation in microchips? They have very interesting random chips that are undocumented, underground, and seemingly random, like the ESP8266 being used in some consumer goods, people noted it, hacked it to run custom software, its essentially a cheaper more powerful and higher energy usage arduino type reprogrammable chip with wifi built in, the company later released an SDK and aruduino studio was also ported. I don't know if there are some wafer that cannot have any defects in them, camera sensors come to mind.

[robbiep]

I’d never heard of Spruce Pine, interesting. I wasn’t able to read the wired article but another article said it wasn’t the silica/silicon that’s the world-beater there though, it’s the quartz for use in crucibles etc?

Also - does the US really have microchip supremacy? The highest tech fabs are non-us (Samsung and TSMC)

[GhettoComputers]

https://web.archive.org/web/20180808115837/https://www.wired... Here you go. Who gave them the technology in the first place and who do they rely on? They did not make it on their own, and the US's reseach, sphere of influence, technology shared in the western world is why these countries were able to advance in advanced electronics. Look at the founder's history in the US. https://en.wikipedia.org/wiki/Morris_Chang Its hard to say what country multinational companies are, you can note their location but does Toyota become Mexican if they assemble their cars in Mexico, Are they American if they assemble it in the US or does Apple become Chinese if they use Foxconn a Taiwanese company in China? If by fabrication location, when TSMC's 3nm plant opens in Arizona, or Samsung opens their 3nm in Texas that mean Taiwan or South Korea has supremacy or the US? The US controls the supply of the best materials, who gets technology, and sells goods like military technology, its lead the semiconductor business and I would have to say without the ideas, and materials from the US, it would not exist.

[smaddox]

If I remember correctly, the silicon used to manufacture transistor-grade wafers is purified to roughly 10 impurities for every billion silicon atoms. Less pure starting stock might increase the cost of getting there, but probably not by too much.

[GhettoComputers]

No, it is not possible. Refinement isn't changing to lower quality, if that was true then every enemy of the US would be refining their own materials. It is in everyone's interest not to rely on a single place for every microchip materials, but the fact that is hasn't happened, and if it didn't incraes the cost by much why hasn't it happened with the US's global enemies? The USSR was never able to gain eqivalence even with the same blueprints and they were not able to be made in bulk.

>Soviet computer software and hardware designs were often on par with Western ones, but the country's persistent inability to improve manufacturing quality meant that it could not make practical use of theoretical advances. *Quality control*, in particular, was a major weakness of the Soviet computing industry.

https://en.wikipedia.org/wiki/History_of_computing_in_the_So...

[freedomben]

Not what you were offering so feel free to ignore this, but I'm super curious about RISC-V. Do you know if any serious attempts are happening to make RISC-V based systems? And if not, do you know why? Is it too raw/un-polished?

[GhettoComputers]

Yes, it has no licensing fees, and its being used in pinepen, some small electronics like calculators, and do you mean dev kits like this? They are arduino like devices with low power edge AI/neural capabilities. https://www.seeedstudio.com/sipeed

On linux, they are making one with an allwinner chip called the D1. https://www.hackster.io/news/sipeed-teases-linux-capable-64-...

RISC-V is not inherently better or more secure, its a different instruction set with no fees, so anyone can make one, its possible to be less secure.

[mhh__]

RISC-V probably has the most "serious" effort of anything other than ARM and X86.

[datameta]

That's a fair estimate, but let's not forget IBM's Power architecture.

[mhh__]

Power is very cool and I want a Power10 box a lot but I'm not sure if it's fair to really decide in it's favour because POWER is basically unobtainable whereas you can actually buy dev boards for RISC-V from SiFive.

[afr0ck]

There is also Sparc and to a lesser extent MIPS. They are more mature than RISC-V and have a decent software ecosystem.

[kayson]

Not my area sorry!

[bullen]

Have you ever used https://www.fossi-foundation.org?

If I had the skills I would immediately investigate how to couple a RISC-V CPU with some open GPU on that platform!

[kayson]

With most open source hardware efforts, like this, it's not really so much circuit design as it is just code. All of the open source efforts I've seen revolve around digital circuits, which are written in some kind of RTL and turned into an actual circuit by completely automatic processes. It's still great, and I fully support them, but there's a massive amount of non-digital that's crucial to getting these systems up and running. Not to mention that even if you have an open source CPU RTL, for example, you'll need access to a closed-source and often NDA-blocked PDK (process development kit), fabrication company, etc. I remember seeing some efforts at open sourcing the PDK part as well, but remember being unimpressed.

[jacquesm]

It's infotainment, not information. I really like the 'indistinguishable from magic' video:

https://www.youtube.com/watch?v=NGFhc8R_uO4

lots longer, but far more informative and less fluffy.

[Aeolun]

When designing circuits, I cannot imagine you lay everything out by hand. Do you have specific sets of pre-made circuits/connections that you just kind of copy paste all over depending on the desired functionality of the chip?

[kayson]

Analog and RF circuits are laid out completely by hand! But there are often a lot of symmetries and repeated structures that mean you can re-use a lot of layout. Also, designs are often copied, reused, and repurposed, so those layouts just get modified to adjust, which saves time.

For large digital circuits (e.g. CPUs), it's all automated. There's a lot of human involvement, but ultimately a computer is placing all the transistors and wiring them together.

[ffhhj]

Is it possible to embed optic fibers and optoelectronic gates along with semiconductor gates? How is the fabrication process different? Probably there are size limitations due to fiber width and paths?

[zsmi]

This is a very active area of research. It's quite technical though so it takes a good amount of study to get into it.

https://en.wikipedia.org/wiki/Silicon_photonics https://en.wikipedia.org/wiki/Integrated_quantum_photonics

[kayson]

I'm not very familiar with the details, but I know this is an active area of research. Generally you use a process thats conducive to optics (like SOI), you fab the regular silicon in some areas, and you have separate process steps to build the optical devices.

[Aeolun]

Hmm, I was fairly certain there were a few steps missing when the smashed rock suddenly transformed into an ingot.

If minecraft taught me anything it’s that ore doesn’t spontaneously turn into ingots.

[lordnacho]

What's the canonical book? I used to know this from my EE days, but it's been too long.

[kayson]

For circuit design or manufacturing?

I haven't been in school for a while, so I'm not sure what's current. I really liked Baker's book - CMOS circuit design. It had a decent overview of the manufacturing process for the perspective of a designer, as well as good introductions to major design topics.

Unfortunately, with modern processes, most of the textbook design equations and learning no longer apply so it becomes as much learning an art as it is science.

[lordnacho]

Both. Ah I think I might have had that book until my parents' basement flooded.

Yeah of course when it comes to how things are actually done it's hard to know without actually working in the field. But I just wanted an overview.

[kayson]

I think the Baker book is good for an overview. I also used Pierret's Semiconductor Device Fundamentals in undergrad. It goes more in depth for device physics than it is a pure manufacturing text, but I recall it also had a nice overview.

[zsmi]

Baker http://cmosedu.com

And Weste http://pages.hmc.edu/harris/cmosvlsi/4e/index.html

are both very good. Weste is used in more Universities but it also has a digital slant to it.

[69Represente]

which company would you invest in?