[ic_dummy]

How are the pn junctions created? The article says I can "optionally" dope the wafers. Why is that optional? Are they doped to create both p and n areas, or just one type? Or are multiple wafers used? Or are areas somehow doped after etching? Thank you for entertaining my dumb software person questions.

[kayson]

This is one area the article did a very poor job of explaining. In some processes, you treat the entire wafer before you get started with the rest of the procedure. One example that does this is SOI (silicon on insulator) processes. Others may not need this "global" doping, and from what I know most bulk silicon cmos processes do not do this.

Then you do the lithography (photoresist developing, etching, etc) to expose specific regions on the silicon that you want to dope to create devices like transistors, for example. So first you might expose all of the p-type transistor (PMOS) diffusion areas and dope them. Then you'd remove all the photoresist, repeat the procedure to expose n-type diffusions and dope that. And so on for the various needs of that particular wafer.

PN junctions are created simply by having p-type doped silicon adjacent to n-type doped silicon. The boundary between the two is the PN junction. In practice what I usually see is a square of one type with a ring around it of the other, but these devices are not frequently used.