[gautamcgoel]

Suppose I want to make a custom ASIC with 20B transistors. I have a lot of money to spend but no semiconductor experience. How do I go about hiring good chip designers? How much $ should I realistically expect to spend on design, verification, and fabrication, respectively? I've heard $20M is the ballpark for a mask on a leading edge node. What is the marginal cost per CPU?

[kayson]

That sounds way too high for mask costs. You're definitely looking at 7 figures, but I don't think they've yet hit 8. Unfortunately the answer to all of your budget questions is: it depends. It's going to scale with the complexity of your requirements. Something like a custom ARM chip with heavily custom machine learning and signal processing, high speed clocking, etc, would probably need a decent sized team and a few years. On the other hand, there are tiny teams in Asia that crank out bitcoin mining ASICs like candy.

I'm going to guess at a number and say you're probably looking at $10-20MM all in.

As far as hiring good designers, you really need the relevant technical background to screen them. Assuming you need a team, I would suggest starting with someone in a director position at a large company with experience in your area of interest. They would be able to more concretely define the project and determine human resource requirements/allocation.

If your ASIC is just large but not complex (meaning lots of repeated structures), and you can get away with just a few strong designers, I would suggest hiring a consultant to help you define the project and screen candidates. EE profs at your local university might be a good start.

Feel free to shoot me an email (in my profile) if you want to describe your project in more depth and I'd be happy to offer what advice I can.

[nwiswell]

> That sounds way too high for mask costs. You're definitely looking at 7 figures, but I don't think they've yet hit 8.

7nm logic mask set costs are estimated at $10.5M. Of course you could always use a slightly less leading-edge node and save a lot of money.

Slide 13:

https://semiwiki.com/wp-content/uploads/2020/03/Lithovision-...

[kayson]

Huh you might be right, if only just. It says it's an estimate, but that probably means 3nm nodes will be >$10MM for sure

[foobiekr]

20B is slightly bigger than the Apple M! (10nm) and slightly smaller than the 32 core Epyc (14nm), which you should consider are both very substantial projects from a headcount, simulation, tools, licensing, etc.

To put it in perspective, a company a friend founded that is doing a very large but very regular ASIC for TSMC 10nm raised twice what you're ballparking and will end up doing another raise before tapeout. Chips nowadays are _expensive_ if you're anywhere near state of the art. The people who do very high performance chips are also very expensive.

But I'm also guessing that unless you're doing a bitcoin hashing chip, AI chip, or GPU, all of which is regular, your scale estimate is probably very off. If you're doing any of those, just don't.

That said, there are SOC vendors who do core plus, so it's possible that if this is just an accelerator, no matter how wide, you might be able to outsource the whole thing.