For those who are not aware, and I think it is important to Note, Canon is not a new entry to the industry. They were actually competing with ASML before they gave up in the early 10s.
They are aiming at 5nm in 2025 and extend it to 2nm in 2027+. I guess in real world terms you can add at least 1 year to it even in the most optimistic scenario.
I dont expect many logic chips will be using it, given the sunk cost involves in all the new and older design with current tools and manufacturing. But if it works it would be very exciting for DRAM and NAND.
Most SOCs are trimmed for cost, which means cheap manufacturing. Especially the system on a chip design for single board computers.
Even RPI5s with the Broadcom BCM2712 which is super high volume is 16nm. If they manage to get 5nm in 2026 at low cost than that's the path to take the SOC crown.
This could even lead to RISC-V SOCs/SBCs at RPI power and price tag (yeah, still dreaming).
High absolute performance (Xeon / Epyc scale), maybe.
High performance per watt, why not all three? Smaller transistors take less power to switch, so they likely can be run at a higher frequency without thermal issues. (Of course, a lot of other design considerations apply.)
Canon "exited" the race earlier than that. Canon makes KrF scanners, but chose not to pursue ArF scanners. Nikon and ASML did pursue ArF (which were introduced late 90s/early 2000s), later Nikon chose to not pursue EUV scanners, leaving only ASML in that market.
Oh and just to clarify, by "Nikon chose to not pursue EUV" I of course mean "the US made sure the japs can't access the relevant technology because they were market leaders at the time".
FTA: “Canon’s nanoimprint lithography — a technology under development for more than 15 years but which the company says is only now commercially viable — stamps chip designs on to silicon wafers rather than etching them using light.”
“there was a reason the 6800 was expensive. It was made using ‘contact lithography’, where the photomask, containing the image that is to created on the silicon die, comes into direct contact with the silicon wafer. This inevitably led, over time, to damage to the photomask, reducing yields and eventually rendering the expensive photomask unusable. Making a low-cost version of the 6800 would be impossible without a more cost-effective manufacturing process.”
Would they still have to make a standard photomask and use that to produce a mold using EUV lithography? At which point a cheaper process could be used for production. ASML would still be in that supply chain, but only for mold production.
> In addition to the technology enabling high-accuracy measurement of positional-deviation information, matching technology enabling alignment with lower-layer patterns is also important. Canon has developed a proprietary matching system that achieves alignment by using laser irradiation to thermally deform the wafer (Fig. 2). This system makes it possible to change the heat input pattern and freely deform the wafer by controlling an ultra-fine mirror group called a Digital Micromirror Device (DMD). Instead of assuming that thermal deformation of the wafer worsens alignment precision as is conventionally thought, Canon has applied an innovative new approach to the alignment (Fig. 3).
This is damn cool (hah)! They use a DMD to deposit packets of heat to different parts of the mold to warp to match the underlying layer it needs to imprint for localized nm level positioning. Bad ass.
With photolithography, what most chips are made with, the resist is developed by exposing it to UV light. A mask is used so that the desired parts of the resist are left behind, and the rest is washed away. Contact photolithography places the mask directly against the silicon wafer because it helps the optics during exposure, but the mask doesn't directly remove the resist.
In nanoimprint lithograhy, a stamp is pressed into the resist on wafer and leaves the desired pattern behind.
The difference is that the resist is removed mechanically instead of chemically.
For the case of chip lithography they'd probably make source masks, copy the first generation a time or two, and use those secondary source masks to produce consumable 'stamps' for production.
Hopefully the stamps maintain sufficient quality across at least a couple batches (50-100+?) of wafers.
Well, the costs of photolithography have skyrocketed recently, so that's a big part of it. I suspect that plus cost reductions for this tech is why it can be viable despite the masks needing to be remade periodically.
Can you give any sense of numbers because my intuition is telling me the process should be a win.
If it takes N days of very expensive process to make a mask and the mask can be used M times with cheaper process, what are the thresholds where it is not cost effective?
While everybody is looking at the SOTA factories, manufacturing is still constrained at the bigger nodes, and bringing the cost down at older processes looks like a worthy goal
Yeah, I definitely think it's worth pushing the boundaries at the far end, but the middle end it would be so cool to see dramatic evolution/price reductions there such that anybody could get an asic made (in a very large stamped node) a la PCBWay/Oshpark services almost.
Also keen to see us build silicon up into the 3rd dimension as far as we can, not stacking chips but just continuing to add more and more layers until z = x = y, similar to 3d printing I suppose, leading edge nodes don't really have the wiggle room for that sort of experimentation.
But a 20mm^2 multi-layer but "flat/traditional" 3nm chip vs a 20mm^3 50nm chunk of silicon layers would be super cool to play with!
Canon stock is basically unchanged and is underperforming the SP500 slightly on the 1Y, is the market wrong or is this not going to do anything? One would think disrupting chipmaking would be more reflected in the stock price.
"One hope of analysts had been that Canon might be able to sell the machines to China, something ASML can no longer do with its advanced tools due to US export controls."