[fennecfoxy]

Yeah, I definitely think it's worth pushing the boundaries at the far end, but the middle end it would be so cool to see dramatic evolution/price reductions there such that anybody could get an asic made (in a very large stamped node) a la PCBWay/Oshpark services almost.

Also keen to see us build silicon up into the 3rd dimension as far as we can, not stacking chips but just continuing to add more and more layers until z = x = y, similar to 3d printing I suppose, leading edge nodes don't really have the wiggle room for that sort of experimentation.

But a 20mm^2 multi-layer but "flat/traditional" 3nm chip vs a 20mm^3 50nm chunk of silicon layers would be super cool to play with!