[scottchin]

Having done my graduate studies in FPGA architecture and software, I can definitely see where the author is coming from. In fact, it seems like the entire hardware development industry has to face the issue of most tools being closed-source. Although I don’t have a solution for the technology specific phases (Place and Route, Bit Stream Generation, etc.), I am actually part of a company that is trying to help solve this problem higher up in the tool chain.

One of the biggest barriers to developing EDA (electronic design automation) software tools is knowing all the nuances of the various hardware-description languages like VHDL, Verilog and System Verilog. We learned this the hard way through our previous startup (later acquired) which built a hardware verification tool.

I don’t want to be self-promoting here, but in case anyone in this thread is interested, we are building a platform called Invio that lets you build your own EDA tools. We try to solve more than just the language support side of things and all of our platform’s inputs and outputs are open standards: Python, TCL, Verilog, SystemVerilog, VHDL, etc. You can look at my profile to find more info, or google “Invio”.

[jjoonathan]

Do you have an offering that would allow me to code up a SystemVerilog->Verilog translation script on a hobbyist budget? I'm stuck coding for my SP605 in Verilog (or VHDL) but I would really like to be able to use structs and interfaces from SystemVerilog.

Coming from software dev it's insane: The $500 devkit doesn't support structs and I would have to pay $1300 to get one that does. Meanwhile C has had structs for 40 years... :(

[elovlie]

I've had similar needs but couldn't find an existing tool, nor a parser on which to build. There are some open source parsers [0], but they don't seem to do preprocessing and hence lose a lot of context.

So I made a parser that might work for your use-case given some work:

https://github.com/svstuff/systemverilog

It works for some fairly big codebases, so I know it's not completely broken. I'm not very proud of the scala code, it's quite ugly in places. But at least there are some tests :p

[0]: this also seems active worth checking out: https://github.com/gburdell/parser

EDIT: added link to other parser.

[jjoonathan]

Thanks, looks promising! My needs are pretty minimal at the moment but it will be both refreshing and educational to give this a go.

Duplicating all the DRAM wires at each and every level of abstraction was just hideous.

[UncleOxidant]

How about using VHDL and records? I think these are synthesizeable outside of ports. VHDL is a much better language from a software engineering standpoint than Verilog.

[jjoonathan]

I know nothing about VHDL -- I vaguely remember hearing someone say it suffered from the same issue so I didn't pursue it. Thanks for the tip!

[UncleOxidant]

VHDL is more strongly typed than Verilog (I consider this a good thing). Sure, it's a bit more verbose, but the language is more expressive than Verilog - allows overloading operators, for example. A nice example of the advantage of VHDL over verilog is that there's a FixedPoint type in VHDL (as of VHDL 2008, I think) whereas in Verilog you're on your own to line up the binary points - very annoying.

[lmm]

aninhumer was (and may still be) doing something similar-sounding with bluespec; you may like to talk to him.