[jjoonathan]

I know nothing about VHDL -- I vaguely remember hearing someone say it suffered from the same issue so I didn't pursue it. Thanks for the tip!

[UncleOxidant]

VHDL is more strongly typed than Verilog (I consider this a good thing). Sure, it's a bit more verbose, but the language is more expressive than Verilog - allows overloading operators, for example. A nice example of the advantage of VHDL over verilog is that there's a FixedPoint type in VHDL (as of VHDL 2008, I think) whereas in Verilog you're on your own to line up the binary points - very annoying.