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by jjoonathan 4077 days ago
Do you have an offering that would allow me to code up a SystemVerilog->Verilog translation script on a hobbyist budget? I'm stuck coding for my SP605 in Verilog (or VHDL) but I would really like to be able to use structs and interfaces from SystemVerilog.

Coming from software dev it's insane: The $500 devkit doesn't support structs and I would have to pay $1300 to get one that does. Meanwhile C has had structs for 40 years... :(
2 comments
elovlie 4077 days ago
I've had similar needs but couldn't find an existing tool, nor a parser on which to build. There are some open source parsers [0], but they don't seem to do preprocessing and hence lose a lot of context.

So I made a parser that might work for your use-case given some work:

https://github.com/svstuff/systemverilog

It works for some fairly big codebases, so I know it's not completely broken. I'm not very proud of the scala code, it's quite ugly in places. But at least there are some tests :p

[0]: this also seems active worth checking out: https://github.com/gburdell/parser

EDIT: added link to other parser.

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jjoonathan 4077 days ago
Thanks, looks promising! My needs are pretty minimal at the moment but it will be both refreshing and educational to give this a go.

Duplicating all the DRAM wires at each and every level of abstraction was just hideous.

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UncleOxidant 4077 days ago
How about using VHDL and records? I think these are synthesizeable outside of ports. VHDL is a much better language from a software engineering standpoint than Verilog.
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jjoonathan 4077 days ago
I know nothing about VHDL -- I vaguely remember hearing someone say it suffered from the same issue so I didn't pursue it. Thanks for the tip!
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UncleOxidant 4077 days ago
VHDL is more strongly typed than Verilog (I consider this a good thing). Sure, it's a bit more verbose, but the language is more expressive than Verilog - allows overloading operators, for example. A nice example of the advantage of VHDL over verilog is that there's a FixedPoint type in VHDL (as of VHDL 2008, I think) whereas in Verilog you're on your own to line up the binary points - very annoying.
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