[elovlie]

I've had similar needs but couldn't find an existing tool, nor a parser on which to build. There are some open source parsers [0], but they don't seem to do preprocessing and hence lose a lot of context.

So I made a parser that might work for your use-case given some work:

https://github.com/svstuff/systemverilog

It works for some fairly big codebases, so I know it's not completely broken. I'm not very proud of the scala code, it's quite ugly in places. But at least there are some tests :p

[0]: this also seems active worth checking out: https://github.com/gburdell/parser

EDIT: added link to other parser.

[jjoonathan]

Thanks, looks promising! My needs are pretty minimal at the moment but it will be both refreshing and educational to give this a go.

Duplicating all the DRAM wires at each and every level of abstraction was just hideous.