[sharkjacobs]

> Developed from design to production in nine months, accelerated by OpenAI’s models

> the use of OpenAI models to accelerate parts of the design and optimization process.

I wish there was more about this. As is I kind of have to assume that this is just meaningless marketing, like saying development was accelerated by Microsoft Office or their 5k LG Ultrafine 40-inch monitors.

Like, if this was as big a deal as it kind of vaguely implies, they would be making a bigger deal of it, right?

[zgao]

Chip CEO here. It really depends on what "design" or "production" means. Does "design" mean that the design was complete? Does "production" mean the beginning of production, i.e. tapeout? If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip. If measuring from concept (no RTL at all, block diagram of architecture) to tapeout, this is an amazing timeline. The truth is probably somewhere in between. A more concrete statement would use actual technical milestones and gates.

[otterdude]

Not a chip CEO, but I read this article and thought that they're working on some kind of application specific chip only for serving models. Similar to how an FPGA can optimize certain tasks.

Given constant weights / biases of a Transformer / DNN you could use pipelining to feed forward calculations through the array one layer at a time. For DNN's with thousands of layers you might see 1:1 speed up per layer channel.

I doubt they would undergo this process for marginal gains.

[xdavidliu]

i don't understand what the second paragraph is saying.

[nine_k]

In very crude terms, AFAICT, if you have a bunch of matrix multiplications, but one of matrices (the one with model weights) doesn't change, you can seriously speed up the computation. One thing is that you don't need to re-fetch the elements of the constant matrix, you can keep it near the ALUs. Then you maybe can detect and ignore sparse / empty blocks by marking them once.

IDK how the custom hardware exploits this; would love to hear any ideas!

[otterdude]

Basically getting around the branch predictor problem with generalized compute architectures https://en.wikipedia.org/wiki/Branch_predictor

[nonethewiser]

>If measuring from RTL-freeze to tapeout, this is a fairly typical (even somewhat unimpressive) timeline (accounting for some unexpected issues) for a large, complex 3nm chip.

Even for a company’s first design?

[hailwren]

I don't think you get the newcomer novelty buff when your val approaches 13 digits.

[formerly_proven]

This isn't Broadcom's first design.

[swiftcoder]

Yeah, "first chip" here likely means they contracted Broadcom (or a firm with similar experience) to do all the heavy lifting. Building out your own in-house teams for this sort of thing is a decade-long project - just look how much inside Apple's early chips was licensed ARM / PowerVR cores

[MisterTea]

Apple didn't have the talent in-house until they bought Intrincity who worked with Samsung on Apple's earlier Arm chips as well. https://en.wikipedia.org/wiki/Intrinsity

[aurareturn]

Broadcom already has a ton of IP for AI SoCs. I'm guessing the hard parts of this inference chip was already designed by Broadcom and OpenAI simply told Broadcom what it wanted. It's likely very similar to Google's TPU.

  Early testing shows that the first-generation accelerator will deliver performance per watt substantially better than current state-of-the-art

What is substantial here? Vera Rubin is shipping in volume later this year and it is expected to be 10x more power efficient for inference than Blackwell.[0] Even if they're already taped out the chip, getting bugs fixed, getting chips manufactured, getting HBM allocation, getting a rack design, hooking them up together, putting them in a data center will likely take at least another 12 months or likely more. By the time this chip is in data centers in volume, they're likely competing against Vera Rubin Ultra or maybe even Feynman.

Personally, I don't think OpenAI should have invested in this project. It's too early for them. They should have focused on models like Anthropic and win there. When they're profitable, they can take on these projects.

The risk here is very high for OpenAI because AI has a hard cap in energy. If you have a gigawatt, you should only install the best chips. If Nvidia's chips are better, then this is a wasted project and likely wasted billions.

[0]https://developer.nvidia.com/blog/scaling-token-factory-reve...

[cptskippy]

Why do you assume Broadcom has a ton of IP for AI SoCs but hasn't done any of the other work around data center scale deployments?

[aurareturn]

They have. That's why OpenAI was able to get a working demo in 9 months. But going from a small scale system to a full fledged data center deployment is likely much harder.

I don't know how much of the things outside of the chip Broadcom has vs Google's proprietary tech that is not shared with Broadcom.

Nvidia's Vera Rubin has 6 unique chips working together in a single rack.[0]

[0]https://developer-blogs.nvidia.com/wp-content/uploads/2026/0...

[threecheese]

I’m just happy to see diversity here; sometimes I feel like Nvidia is going to eat the world, with buying other fabs and branching out - or up, I guess - from chips and racks to models, frameworks, and end user stuff.

[Aurornis]

The hardware description languages (HDL) used in chip development are like programming languages. The existing models understand them and can do a lot with them. You don’t need to have separate, specialty models designed for this work to use LLMs in chip design workflows.

Design verification also involves a lot of traditional programming which benefits from LLMs.

So it’s not meaningless at all. You could download some of the open source chip design software today and the LLMs could even help you get started on your own tiny chip if you are so interested.

[knicholes]

I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing. The project was a big red arcade button that plays the "ah-my-groin.mp3" when pushed (from Simpsons). It did cool work on saving battery life, and the 3d enclosure was awesome, but yeah, I'm convinced I'd have to do another version or two of the custom chip until it came back right. I used a Blender MCP for the 3d modeling. I used a KiCAD MCP server for the chip design/validation.

I think we're not there yet. I've been meaning to look at this flux.ai to see if it has the prompts/workflow worked out better than what I was able to cobble together in a few hours. Maybe Alteryx's MCP server would have been better. I'll try that this weekend for another board I've got.

[Aurornis]

> I tried making a button using Claude entirely (including the 3D printed enclosure) and it effed up pretty hard with the traces and the header spacing.

PCB design and 3D CAD design are different topics.

Hardware Description Languages are closer to programming languages than CAD. Look at some Verilog to get an idea - https://en.wikipedia.org/wiki/Verilog

[knicholes]

Right. KiCAD for PCB design. Blender for 3D CAD. Oh, are you saying I should have used something other than the KiCAD MCP server for better results?

[VorpalWay]

Designing circuit board and 3D models (even using something like OpenSCAD) is a very spatial process today. You are dealing with coordinates one way or another.

This is very unlike how FPGA and (I assume) ASIC is done. That is more like a traditional programming language but everything happens all at once (no sequence of statements outside tests, if you need that you have to write a state machine yourself). You define logic expressions between signal, add stateful latches, etc. But you never specify the physical layout.

Instead you feed your description to a tool that acts a constraint solver/optimiser that computes the layout for you (this is for FPGAs called synthesising IIRC, it is akin to a compiler). Typically quite slow, even for small circuts like we did at university it took minutes, and for large circuits it might easily days.

Now, this raises the question, what if you design a PCB net list using AI, but then use traditional autorouting and layout? I believe that can also be done, but I have no experience designing PCBs, so I don't know how well it works.

[quadrature]

VHDL is not a language for spatial design. Its more akin to a programming language with circuit semantics.

[dcrazy]

They’re saying that VHDL is an entirely different concept than physical modeling.

[giancarlostoro]

You're comparing apples and oranges.

[cwillu]

Meta: can we not downvote people who are clarifying what they're saying and asking questions, even if they're wrong about something, if the content isn't otherwise objectionable?

[baq]

I didn’t downvote, but the OP is either a troll or someone who doesn’t want to notice he doesn’t know what he’s talking about. Either way we want less of that on HN.

[tamimio]

One (kicad) make the board, the other (blender) make the casing for it. Both are “hardware” but is electronics and the other is mechanical. Electronic one AI can do a good job, I can’t wait for it to fully built the whole circuit for you based on your specs.

[rpcope1]

PCB layout is an art, and doesn't seem to map well to LLMs (I tried for shits and giggles recently). Claude in general, kind of like code, does a lot of redundant belt and suspenders stuff in the schematics it generates (if it can generate them at all). It's one of those things that's really not there yet outside of the simplest designs.

[ses1984]

The question isn’t whether or not they employed a particular tool, the question is how big of an impact did it have.

[nradov]

Most HDL code is locked up behind corporate firewalls and not available as training data. While LLMs can handle it to an extent there's a lot of room for improvement. I'll bet that OpenAI and their competitors are racing to license this IP from major hardware vendors in order to compete in the chip design vertical.

[tonfa]

Does it work better when using compiler based ecosystem (e.g. https://github.com/llvm/circt)

[doxeddaily]

This reminds me of the dude on youtube building a chip fab in his shed.

[IshKebab]

> The existing models understand them and can do a lot with them.

In my experience they are not especially good at SystemVerilog. There's a lot of knowledge about it that is locked behind paywalls and it's very niche.

My guess is the "from scratch" here is quite the exaggeration. Otherwise why did they need Broadcom?

[petra]

There was something similar to c\c++ for hardware design. Maybe it could work better with LLM's with some training?

[aseipp]

Not having a free toolchain that can actually handle the real language has probably been pretty bad on the downstream public knowledgebase. Hopefully Verilator can eventually close that hole, and there can be more high-quality designs and codebases incorporated into future models. Claude is at least good enough to write SV that triggered a compiler crash or two. :)

[whynotminot]

Doesn’t Broadcom bring a lot more to bear here than just Verilog? Including relationships with the actual fabricators.

[dofm]

Right. There are two possible meanings and shades in-between:

1) OpenAI genuinely have AI technologies that can improve chip design (bold, unlikely claim, needs evidence)

2) OpenAI designed test/verification models and kernels that could be run on the simulated hardware to test its performance

As you and others have said, it's hard to trust when they are happy to write something that could easily only mean the latter but sounds like the former.

[lovasoa]

3) The engineers working on the chip used ChatGPT from time to time.

[fl4regun]

at the hardware company I work at, people are now using claude code and developing skills for it to do basic stuff like triage or do initial debug on failing tests, search for potential causes in RTL, generate skeleton documentation for designs etc

[dofm]

But isn't this rather the ordinary product of an LLM, now?

Is it worth the claim that they are making in a press release?

[Catloafdev]

I'd be shocked if it was anything more than this.

[changoplatanero]

Browsing openai's job postings in the past few months is enough to contirm that it's more than this. They are for sure making serious efforts at building ai for chip design.

[xnx]

Impossible to know. Could be fake/aspirational roles to impress investors with their grand vision.

[NitpickLawyer]

Jesus. This is tinfoil hat territory now. Why would they fake something like that? ANY company in this field would try to become free from nvda. Goog has done it already, amazon has their own thing, so it can be done. Not saying they'll 0shot this vertical, but ffs, they don't need to fake anything. They are making an effort, and it would be insane to think they aren't. Might work, might not work, but to even think that the effort is fake is going too far.

[signatoremo]

Do you have inside knowledge?

[reducesuffering]

From time to time? Lol you must realize, frontier lab eng are using Codex/Claude-Code 99% in loops, on models the public doesn't have access to. Why? Because it works. Just a matter of time before humans are out of the loop and what comes next is a black hole

"The future is here, it's just not evenly distributed"

[wongarsu]

Or OpenAI accelerated the design and optimization process by summarizing emails exchanged during the design and optimization process, or made it possible to ask an AI questions about meeting notes

[Aurornis]

> 1) OpenAI genuinely have AI technologies that can improve chip design (bold, unlikely claim, needs evidence)

Chip design languages (HDLs like Verilog or VHDL) are well understood by LLMs. They don’t need specialty tools to use GPT-5.5 or other LLMs with them.

You could even try it yourself with open source chip design tooling if you wanted to see it.

[dofm]

Yes, obviously. But do we think LLMs without access to proprietary information do a better job with them than Broadcom's human experts or existing proprietary tools at this level of operations?

It is still a bold claim and it still needs evidence.

We would obviously get a bit more of the evidence if it were to be more useful for the upcoming IPO than this rather open-ended, reinterpretable phrasing.

[dpe82]

I don't understand why you're getting downvoted.

I've used GPT-5.5 and Opus both for FPGA design with good results. We built a lot of tooling around it to help the models, but even without that they're definitely capable of designing digital logic.

[dmitrygr]

My guess: it is that those who KNOW the subject realize that LLMs suck at it, and those who do not, do not realize it, since their output is plausible, and sometimes even works.

This actually plays out across every field and is well documented. An expert can recognize the hallucinations and bullshit coming out of LLMs, while non-experts see plausible output and do not know enough to know it is BS.

[wmf]

https://dl.acm.org/doi/10.1145/3785362

https://developer.nvidia.com/culitho

https://www.synopsys.com/blogs/chip-design/analog-layout-syn...

https://arxiv.org/abs/2302.06415

[etempleton]

I feel like they would be very specific if it was no.1.

[oceanplexian]

> OpenAI genuinely have AI technologies that can improve chip design (bold, unlikely claim, needs evidence)

Why is that a bold and unlikely claim?

Are you saying that AI, which has been proven to cure diseases, solve our hardest math problems, write complex computer code and generate entire generated worlds and HD video from a simple prompt would somehow be like, my bad, I guess I can't design chips?

[smokel]

> solve our hardest math problems

We're not quite there yet :)

https://en.wikipedia.org/wiki/List_of_unsolved_problems_in_m...

[dofm]

> Why is that a bold and unlikely claim?

Because they could have offered even slightly more evidence.

[cess11]

Because then they'd likely have stfu and outperformed Intel, Nvidia and AMD, or at least one of them.

They're burning more cash than pretty much anyone else and doesn't have anything public that looks like a matching revenue stream so they probably need one very badly.

[scrollop]

Perhaps they used gpt 5.5 mini to draft emails. Create a coffee schedule.

[nickvec]

I feel like "the use of OpenAI models to accelerate parts of the design and optimization process" just means that engineers were using ChatGPT to sanity check their designs and suggest potential optimizations, though that's just my take (and I'm quite cynical about AI marketing in general!)

[SCUSKU]

My girlfriend works at Broadcom doing chip design, and based on what she's told me they JUST got claude code like 3 weeks ago, so I really doubt this means anything beyond them vibe coding some scripts or something...

[blitzar]

> the use of email, spam filters and spellchecker to accelerate parts of the design and optimization process

honestly you don't realise how much more efficient it is until you are stuck using the wrong flavour of outlook, the spam filter breaks or sloppy spelling, punctuation and grammar force you to clarify details needlessly.

[nixon_why69]

There is a lot of verilog out there, it's pretty feasible that they had AI assistance writing more to design their chip.

It doesn't have to be revolutionary, it could just be AI-assisted design and lined up well enough with their operations for a custom ASIC to be worth it.

[KeplerBoy]

Also there's some much boilerplate around everything. Writing a testbench with codex is extremely feasible. This is the kind of verifiable feedback loop the agents shine at.

[figassis]

VHDL, VLSI are well documented languages, with well build test and verification frameworks and harnesses. Even just by iteration you could get there if you have the money to pay for it.

[HarHarVeryFunny]

I would assume they've already made as big a deal of it as they can without outright lying too much. Read the rest of the press release.

FWIW, Google is now on their 8th generation TPU, having put out the last 4 generations on a 1-year cadence.

[FanaHOVA]

NVIDIA already designs most of their chips using AI. Why would you assume it's meaningless marketing?

[fecal_henge]

Perhaps because they are suggesting what they are doing is novel.

[DoctorOetker]

novel to whom, the reader or the industry?

something can be non-novel in the industry, yet novel to the reader, at which point it is useful ... for such readers.

[seydor]

realistically, how hard are AI accelerators to design?

[xnx]

AlphaChip is what a chip design with AI is. I'm very suspicious that OpenAI has anything like this or they would be bragging about it.

https://deepmind.google/blog/how-alphachip-transformed-compu...