[sand500]

For a mass produced product, why waste die space on RISC-V cores that can only be used instead of the Cortex cores? Why not just use that die space for more ram or another ARM core? Doesn't it make sense to sell a variant that is entirely RISC-V?

[coder543]

https://x.com/wren6991/status/1821582405188350417

Supposedly it didn’t require any measurable amount of additional die space, because other things constrained the minimum size of the die (like the I/O pads), according to one of the Raspberry Pi engineers.

An additional ARM core would have required significant changes to the crossbar. Right now, only two cores can be active, not three.

[sand500]

Does that mean the RISC-V cores are super low powered?

[coder543]

It just means that the die already had to be large enough to physically fit the number of pin pads that they wanted to have. It doesn’t really say anything about the RISC-V cores. They could be big or small. But these do seem to be almost as powerful as the ARM cores, based on what people have said. (I still want to see more benchmarks.)

[numpad0]

If I were to guess, they probably concluded that `cumulative wasted manufacturing cost` < `engineering fees and costs of maintaining two entirely different chips`.

I think this type of pseudo-wasteful design is not unheard of when manufacturer had two markets to deliver to that had substantially different processing, but not I/O, requirements, as well as when some of major features in already manufactured chip didn't work out and ways to offset losses would be nice.

[cjbgkagh]

Wild-ass guess; but I assume there is a lot of overlap in the functionality between the type of cores which would mean only a small amount of extra space is required for the additional RISC-V instruction set support as opposed to having distinct CPU cores.

[Y_Y]

They're sharing silicon? That's cool if true.

[BertoldVdb]

It's very unlikely IMHO. Both the RISC-V and the M33 are very tiny in die area, compared to for example the 512kB RAM, or even compared to a few bond-pads.

Making a single core with two instruction decoders but a shared register file, caches, prediction logic and ALU would make sense for a very high-end application processor type core, but not for these small devices. You would also need an instruction set license from ARM for that, vs just licensing the M33 netlist.

[cjbgkagh]

That makes sense, it seems that my guess was wrong, thanks

[coder543]

I highly doubt it. I agree it would be cool if it were true.

[wkat4242]

Yeah or allow all 4 to be used at the same time