It's very unlikely IMHO. Both the RISC-V and the M33 are very tiny in die area, compared to for example the 512kB RAM, or even compared to a few bond-pads.
Making a single core with two instruction decoders but a shared register file, caches, prediction logic and ALU would make sense for a very high-end application processor type core, but not for these small devices. You would also need an instruction set license from ARM for that, vs just licensing the M33 netlist.
Making a single core with two instruction decoders but a shared register file, caches, prediction logic and ALU would make sense for a very high-end application processor type core, but not for these small devices. You would also need an instruction set license from ARM for that, vs just licensing the M33 netlist.