[cjbgkagh]

Wild-ass guess; but I assume there is a lot of overlap in the functionality between the type of cores which would mean only a small amount of extra space is required for the additional RISC-V instruction set support as opposed to having distinct CPU cores.

[Y_Y]

They're sharing silicon? That's cool if true.

[BertoldVdb]

It's very unlikely IMHO. Both the RISC-V and the M33 are very tiny in die area, compared to for example the 512kB RAM, or even compared to a few bond-pads.

Making a single core with two instruction decoders but a shared register file, caches, prediction logic and ALU would make sense for a very high-end application processor type core, but not for these small devices. You would also need an instruction set license from ARM for that, vs just licensing the M33 netlist.

[cjbgkagh]

That makes sense, it seems that my guess was wrong, thanks

[coder543]

I highly doubt it. I agree it would be cool if it were true.