[ineedasername]

Sounds like spending a few hours a month learning an HDL could be a good long-term career decision.

[nsajko]

I think the right way isn't "learn a HDL", it's "learn digital electronics design". Hardware description languages enable succint hardware description, but it's still necessary to keep an image of the actual hardware in mind.

[ip26]

HDL is really just ascii schematics.

[PoachedSausage]

I often find it easier to grok things like circuits and logic visually, certainly when in circuit design/PCB mode.

Does anyone know of any open source software for taking smallish chunks of Verilog/VHDL and making a visual representation/schematic?

[nobodywasishere]

I wrote a small blog post about using netlistsvg, yosys, and ghdl to make block diagrams for VHDL here: https://nobodywasishere.github.io/netlistsvg/

[PoachedSausage]

Thanks. Very useful.

[minetest2048]

yosys with yosys show command can do it for Verilog: http://www.clifford.at/yosys/files/yosys_appnote_011_design_... I found it really helpful to see what a chunk of Verilog code would look like after synthesis.

There is an online version at here: http://www.clifford.at/yosys/nogit/YosysJS/snapshot/demo02.h... which uses YosysJS. Hopefully someone can port Compiler Explorer UI to this

[mhh__]

https://digitaljs.tilk.eu/ also this

[PoachedSausage]

I had a feeling yosys might do it somehow. Thanks.

[seabird]

You're going to need to commit a lot more time than that. HDLs and the surrounding concepts have key fundamental differences from software that a lot of developers have a hard time stomaching. That's why high-level synthesis is the FPGA industry's City of El Dorado; software developers would be able to create acceleration designs without having to build up a fairly large new skillset.

[imtringued]

I've never understood this argument. The change in mindset is extremely small. It's merely a matter of awareness. High level synthesis can work just fine if you don't go overboard with constructs that are hard to synthesize. There is no fundamental reason why a math equation in C should be harder to synthesize than the Verilog or VHDL equivalent.

[mhh__]

> math equation in C

I think it's the bits around the outside of the (say) math kernel which will trip up an "ah it's just like C!"-thinking programmer.

[pjmlp]

Except that part that electronics must also take physics into consideration, and if they plug into some kind of analog circuits even more so.

[rowanG077]

I think HLS is oversold. It's not that hard for software guys to learn some digital logic and write an accelerator. One or two weeks and it shouldn't be a problem. Where the real problems lies is in the tooling. You can't learn that in one or two weeks. You first need to damage your brain to be able to handle it.

[ineedasername]

I'm assuming that if public knowledge of AMD's efforts are at the patent level, it will be a few years before there's much to work with, by which point you'd have a solid foundation from which to accelerate your learning.

[Nullabillity]

The dataflow dialect of VHDL instantly felt really natural to me, coming from FRP (among a bunch of other stuff).

Of course, using it in industry is presumably pretty different from using it for a few school courses.

[deelowe]

Anyone who is considering this, make sure you learn digital circuits first.

[efferifick]

While sibling comments mention that it is probably wiser to learn digital logic before HDL (and I agree with them), I think it is important to also consider that there is now High Level Syntehesis where programming languages similar to C (e.g., OpenCL) can compile to VHDL. HLS may lower the barrier for programmers to take advantage of FPGAs. However, whether the design can compile to fit the constraints of the FPGA available is another question that I do not know the answer.