[ip26]

HDL is really just ascii schematics.

[PoachedSausage]

I often find it easier to grok things like circuits and logic visually, certainly when in circuit design/PCB mode.

Does anyone know of any open source software for taking smallish chunks of Verilog/VHDL and making a visual representation/schematic?

[nobodywasishere]

I wrote a small blog post about using netlistsvg, yosys, and ghdl to make block diagrams for VHDL here: https://nobodywasishere.github.io/netlistsvg/

[PoachedSausage]

Thanks. Very useful.

[minetest2048]

yosys with yosys show command can do it for Verilog: http://www.clifford.at/yosys/files/yosys_appnote_011_design_... I found it really helpful to see what a chunk of Verilog code would look like after synthesis.

There is an online version at here: http://www.clifford.at/yosys/nogit/YosysJS/snapshot/demo02.h... which uses YosysJS. Hopefully someone can port Compiler Explorer UI to this

[mhh__]

https://digitaljs.tilk.eu/ also this

[PoachedSausage]

I had a feeling yosys might do it somehow. Thanks.