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by chasil 23 days ago
Heat is a huge problem?

Heat radiation elements must be designed as part of the structure?

Sophie Wilson has famously said how easy it is for active silicon to get hotter than a nuclear reactor.

4 comments

Heat is exactly why this is useful. A very large amount of power draw is due to the physical size of circuits. This monolithic 3D stacking should result in smaller wires for decreased parasitic capacitance. SRAM is probably the biggest winner in some respects. The paper suggests they can make SRAM smaller, and given most of a modern CPU die is SRAM I would be shocked if that wasn’t a huge thermal win alone, either by adding more cache or by reducing the size of the core or both.

I’d be interested to see if you couldn’t throw diamonds at the heat problem though. There was some recent work done suggesting diamond could help a lot with heat, but I’m unsure if it would work here.

Yeah; without Dennard Scaling, cooling becomes an issue, they're useless to laptops, and you can only double or triple density vs a regular chip before they draw too much power for a home outlet.
Typically this is used to stack many layers of memory on top of one or two layers of compute.
> Sophie Wilson has famously said how easy it is for active silicon to get hotter than a nuclear reactor.

The center of a fuel rod in a PWR reaches more than 1000 C.

Perhaps Wilson was talking about the thermal power/area of chips vs. the surface of fuel rods. I believe the former can exceed the latter.

Poorly designed or managed chips can reach the point that hot spots in the silicon literally melt, which happens at ~1400C. Thermodynamics sitting on an insulator (relative to the metal portions of the chip at least) on very small scales is very weird and can reach wild spot temps.

That's why chip thermals is its own whole subfield of physical design.

Sure, but the center of a PWR fuel rod reaches high temperature in normal operation. Uranium dioxide is not a great conductor of heat.

Chips have the advantage that the workings are right at the surface, mere microns from it. So the heat can easily get out. The power density in that thin surface layer can be very high. Perhaps similarly, the power density of a PV cell can be very high, if one just looks at the active layer where light is being absorbed. In CdTe this layer is < 1 micron thick. The energy delivered over the life of the cell per atom in this layer can approach that of nuclear reactions.

I will add that if we're talking about abnormal operation, say in a reactor meltdown, uranium dioxide can reach its melting point, 2865 C.

Anyway, it's a promising comparison, since the core of a PWR can reach volumetric power density of ~100 MW/m^3 (and probably higher in naval reactors). Servers can potentially be made very compact.

The amount of current that can be pushed through a thin silicon die is just wild.
I think of that every time I watch my GPU hit 440W sustained power draw on a die that is ~23mm square.

Which comes out to be about 831kW per square meter and the cooling solution keeps it at 60-63C even under that load (while noticeably warming my office since it's effectively dumping the same as one bar on a two bar electric heater).

As a species, we got really good at engineering.

I know nothing about your GPU, but it's probably at around 1V core voltage, so this is hundreds of amps.
Not far off, stock under full load is 1.15V (1150mV).
> active silicon

This is not necessarily a functioning chip.