[dlcarrier]

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio.

Getting more efficient output is a nice bonus.

[st_goliath]

> ... don't require absurdly bloated development environments.

Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work:

You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version tough, that has some major UI bugs. You want to program a HerpSoft PLC? You need EasyHerpes IDE! What, command line toolchain? Text editor? You must be completely insane!

It's been somewhat of a personal fight against windmills for me back then. That, plus suggesting that we are actually developing software and the C/Assembly/VHDL maybe shouldn't be an undocumented, tested-only-once pile of spaghetti based off a circuit diagram inside one guys head (and no, a 50 line comment block with a German transcription of the code below is not documentation).

[Ygg2]

> and no, a 50 line comment block with a German transcription of the code below is not documentation

You had it good back then. Now it's a one-line comment in Chinese. Line is 300 characters wide. /Yorkshire men skit.

[st_goliath]

Now that's funny. The irony here is that, besides German (native), I do speak some HSK4-ish Mandarin as a 3rd language. A few years ago, a single line Chinese comment next to a blob of magic hex values did help me figure out a bug in a touch controller driver :-)

[Aurornis]

It's not that the official tools are the only way to work with parts.

It's that they're the only vendor supported method of working with the parts. If you build your product with an unsupported toolset and something doesn't work, you need to be prepared to reproduce the issue in the vendor support toolchain if you want support.

People coming from desktop and mobile development roll their eyes at this because they aren't coming across bugs in their x86-64 process or M1 Silicon that haven't already been patched over by some combination of microcode, the OS, and the toolchain. Everything works as expected.

Not so in the world of embedded. On modern complex systems, vendor involvement can be a critical part of the development process. Many of the products you have in your house like your router, Wifi gear, and IoT devices were probably co-developed to some degree with the hardware vendor. Starting with the vendor-provided reference design gets you to market much faster, even though you often could forge your own path with a separate toolchain and start from scratch.

It's still this way even in MCU development. You can go out and develop something like an STM32 system completely without STMicro's tools, but it's much easier to start the project in STMicro's tools and copy over the parts you need for setting up everything from clocks to peripherals, then to maintain a skeleton project in the official tools in case your separate toolchain starts acting funny.

[mrheosuper]

>It's that they're the only vendor supported method of working with the parts

And it's because those engineers do not demand. "I Want something easy to use and has GUI, not some Terminal command line"

[ACCount37]

It's much better in microcontrollers. Almost everything can now be handled with VSCode and some open source compiler toolchains.

PLCs and FPGAs are still pretty damn bad though.

[f1shy]

> Is it still that bad?

IMHO yes, if not worse.

Working now with some advanced devices from Xilinx (using very expensive top-line SoC. If you change version of the Vivado tools, you have to basically start again from 0 your project. Is a complicated mess because of matching of the OS in the ARM controller and the FPGA part…

[robinsonb5]

One thing I will say in favour of the Gowin IDE - it does seem to be much more lightweight than the larger vendors' tools. For smaller designs it will often go from zero to bitstream in less time than Quartus or Vivado would have taken to even start synthesizing.

[dreamcompiler]

It's that bad. FPGA designers on my team would routinely start a Vivado job and come back 8 hours later (because that's how long it typically took) and discover Vivado had crashed.

Vivado is expensive, bloated, buggy garbage.

[wucke13]

I have dedicated a large chunk of my (arguably short) professional career on improving upon this, mostly in the safety critical software domain. What was your experience back then, what made you leave ultimately, and what do you do now?

[adwn]

As much as I wish this would come true, there's little chance for a full, end-to-end open source toolchain for Xilinx or Altera FPGAs that's competitive with the vendor tools. The reason for this is that there's no publicly available documentation of the signal routing configuration or the bitstream format, which are required for the final two steps in the chain. I don't see the two market leaders releasing this information anytime soon, and reverse engineering it from the data files is probably rather difficult.

The synthesis discussed in the linked page is one of the earliest steps, and from the point of view of open source implementations, the simplest one, because all necessary information is freely available.

[aappleby]

"there's no publicly available documentation of the signal routing configuration or the bitstream format"

Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

[robinsonb5]

The reverse engineering efforts are impressive (though as I understand it, limited to Xilinx series 7 and Cyclone V) but without robust and reliable timing data to go with the rest of the chip data, they can't give you the same level of confidence that a design will work across a range of a devices and operating conditions.

[amirhirsch]

For the curious: the process of discovering the logic and route timings for an FPGA device is to use ring oscillators (three series inverters) and compare counters against a known clock. Place the inverters all over to test every LUT, and use every routing path to test each path's timing.

[adwn]

> Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

Please provide a source for this claim. Yosys, for example, can't route [1] designs even for Xilinx 7-series devices, and that architecture has been introduced 15 years ago.

[1] Not to be confused with synthesis, mapping, or placing, all of which come earlier in the flow, and for all of which sufficient information is public available.

[robinsonb5]

Yosys doesn't do place-and-route - typically that part would be handled by nextpnr, and there's an experimental fork of that for Xilinx series 7 devices: https://github.com/openXC7/ (full toolchain)

It works well enough to build a working litex RISC-V SOC capable of running Linux, for the QMTech Kintex-7 325T board.

I don't think the Cyclone V project has got as far, but I could be wrong. (It kind of slipped off my radar after I realised I was spending way too much time on Discord and purged all but a very few servers to reduce my distractions.)

[dlcarrier]

They seem to be pushing in that direction. Here's Altera's latest: https://github.com/OFS

[SuperMouse]

Most FPGA vendor tools can be used from the console. But they are very fat.

[polalavik]

I know of a few vendor tools whose application size is measured in the multi-hundred of GBs

[topspin]

How does that happen?

When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.

[RossBencina]

I'm not saying the tools aren't bloated, but I believe that a lot of the size (sorry, can't quantify right now) are the datasets for each and every FPGA model that the tool supports. This includes, among other things, timing information for every wire in the chip. You really only need the files for the device that you are targeting and you do have the option to install only that, or you can install larger groups (e.g. same family, same generation), all the way up to installing every device that ever existed that the tool supports. That's how you get to hundreds of GB.

[goku12]

Are you sure about that, or is it just a guess? If that is the case, how will the open source toolchains avoid the same problem when they eventually become the industry standard? (I can imagine something like a software repository for serving device-specific information on demand.) Are they planning anything right now?

[adwn]

Xilinx toolchain installations used to include a file which was just the concatenation of the license files of every single open source library they were using somewhere inside any of their own software. Now if you installed two or more components of their toolchain (for example, Vivado, Vitis, and PetaLinux) into the shared installation directory, this same file was installed several times as well. Together, they made up something like 1.5 GiB alone.

I think they've fixed this only a year ago or so.

[ithkuil]

Seems a good candidate for a file that can be kept in a compressed form

[mschuster91]

Welcome to modern development lol. Try to refactor it and get an answer of "no money for testing".

On top of that, the "agile" mindset all too often also means there is no coherent vision where the project should go, which can and does lead to bad fundamental architecture decisions that need extensive and expensive workarounds later on.

And yes, there have been people describing exactly that in ASML [1], although the situation seems to have improved [2].

[1] https://news.ycombinator.com/item?id=23363938

[2] https://news.ycombinator.com/item?id=39465412

[SuperMouse]

Xilinx and Altera want to talk to you :-)

[tverbeure]

The installation can be around 100GB, which is a lot, but you have to distinguish the build part from the IDE. I hardly ever use the IDE and just use a Makefile.

The open source tools still lack too many features to be useful for non-hobby development.