[adwn]

> Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

Please provide a source for this claim. Yosys, for example, can't route [1] designs even for Xilinx 7-series devices, and that architecture has been introduced 15 years ago.

[1] Not to be confused with synthesis, mapping, or placing, all of which come earlier in the flow, and for all of which sufficient information is public available.

[robinsonb5]

Yosys doesn't do place-and-route - typically that part would be handled by nextpnr, and there's an experimental fork of that for Xilinx series 7 devices: https://github.com/openXC7/ (full toolchain)

It works well enough to build a working litex RISC-V SOC capable of running Linux, for the QMTech Kintex-7 325T board.

I don't think the Cyclone V project has got as far, but I could be wrong. (It kind of slipped off my radar after I realised I was spending way too much time on Discord and purged all but a very few servers to reduce my distractions.)