[robinsonb5]

The reverse engineering efforts are impressive (though as I understand it, limited to Xilinx series 7 and Cyclone V) but without robust and reliable timing data to go with the rest of the chip data, they can't give you the same level of confidence that a design will work across a range of a devices and operating conditions.

[amirhirsch]

For the curious: the process of discovering the logic and route timings for an FPGA device is to use ring oscillators (three series inverters) and compare counters against a known clock. Place the inverters all over to test every LUT, and use every routing path to test each path's timing.