[alephnerd]

Interesting but complementary foray into owning the end-to-end pipeline of chip design, fabrication, and packaging - especially for embedded use cases.

MIPS has also hitched it's horse to RISC-V now, and I am seeing a critical mass of talent and capital forming in that space.

[kragen]

The critical mass of talent and capital forming in the RISC-V space happened in 02019 at Alibaba: https://www.cnx-software.com/2019/07/27/alibaba-unveils-xuan...

AFAIK MIPS still hasn't shipped a high-end processor competitive with the XuanTie 910 that article is about. And I think the billions of RISC-V microcontroller cores that have shipped already (10 billion as of 02022 according to https://wccftech.com/x86-arm-rival-risc-v-architecture-ships...) are also mostly not from MIPS.

[nine_k]

(BTW why do you write years with a leafing zero? Do you expect these post to still matter past year 9999?)

[dcminter]

...and if he does, why does he then consider the year 99999 to be out of reach? As I understand it the idea is to promote "long term thinking" but I really don't see how this affectation is actually supposed to achieve anything beyond mildly irritating/confusing the reader.

At least the Long Now Foundation stuff comes with that context built-in.

https://longnow.org/

[ndiddy]

Good point, I will start the Longer Now foundation and start adding two zeroes to the front of all my years.

[hypercube33]

This whole line of conversation and use of the leading zero reminds me of The Church of MOO from the old internet.

[dcminter]

Huh, I know about Bob Dobson et al, but MOO-ism somehow escaped my notice back in the day.

http://textfiles.com/occult/MOOISM/

I have some retro-reading to do.

[garblegarble]

off-topic but: I've noticed you prefix years with a zero in your HN comments. First I thought it was just a typo, but I see you've made several comments like that. Is there some significance, or are you just raising awareness of the year 9999 problem?

[acdha]

It’s the Long Now Foundation’s convention - a bit cultish but harmless.

https://longnow.org/ideas/long-now-years-five-digit-dates-an...

[rrakow]

I think that's some "Long Now Foundation" meme.

[dcminter]

That. Personally I think it's performative nonsense, but you have to admire the commitment to it.

[kragen]

It doesn't require any special commitment because it doesn't cost me anything. Certain people do post a lot of really boring comments about it, but I'm not the one posting those comments, and I don't care about those people's opinions, so I don't care.

I don't believe I'm actually doing those people any injury, so while they're obviously free to continue requesting different formatting of my posts, I'm free to ignore them.

I think it's important for people to be able to complain about things that bother them, for the reasons described in https://news.ycombinator.com/item?id=44501817. In that thread, we were discussing a different commenter requesting that an author please not use AI for editing his own books, although the request was made in a particularly obnoxious fashion. Consider "Please don't play your music so loud at night", "Please don't look at my sister", or "Please don't throw your trash out your car window". But "please format your dates differently" doesn't seem like a very important request, even if it were phrased politely, to the point that it makes me (and, as I've seen, others) think less of the people who are making it.

If my date formatting really bothers them, they're free to stop reading the site. After having looked at their comment histories, I wish some of them would, because the only thing they ever post are similarly vacuous complaints. If people had to choose between reading a site where I posted and they didn't, and a site where they posted and I didn't, 100% of people would choose the former. (Others do occasionally post something worthwhile, but nothing that inspires me to wonder how I could earn their admiration.)

So, these days, I can easily ignore it.

Especially the day after this comment of mine got voted up to +151: https://news.ycombinator.com/item?id=44491713

[avhception]

Every time I encounter it, I think to myself: ah, that guy again. Always brings a little smile to my face. Keep it up!

[dcminter]

> I don't care about those people's opinions, so I don't care.

This was stronger before you edited in the longer paragraphs telling us that you look through their comment histories.

Look, you do you, but I'd rather hear your passionate promotion of the leading zero approach since you apparently know it irritates people.

Edit: PS Isn't it interesting that the comment that you are justly proud of doesn't have any dates in it? :)

[kstrauser]

I suspect it’s counterproductive, though, like deliberately not using pronouns and always referring to someone by name. The intent might be to draw attention to the author’s cause, but it’s more likely to come across that the author just writes weirdly.

[dcminter]

Eh, I also think it's harmless, and lends a certain "brand" to their posts - which are usually quite good otherwise. Better to be weird than dull, right?

[Findecanor]

It was some time ago that MIPS did announce that they had competitive RISC-V cores and had signed customers for them: LG and in the automotive sector. I'd think those should be taped out by now, but who knows...

I think the C910 looks better on paper than it performs in practice. I hope that isn't the case for MIPS.

[kragen]

Do you have any details?

[monocasa]

Adding to what was said, it also suspiciously looks like a MIPS core with a RISC-V frontend strapped to it sort of like Qualcomm did with their Nuvia AArch64 core. Particularly stuff like the soft fill TLB from m-mode looks just like MIPS coprocessor 0.

[ajb]

There's nothing especially wrong with using an existing backend design and transitioning it to another ISA; a number of teams did that from mips->arm and had success with the result. Of course, if you ship too early you may be missing some features.

[monocasa]

> a number of teams did that from mips->arm and had success with the result.

Do you have any examples? Apple Silicon cores took pieces of the pwerficient cores, and everything else I know of either tweaked an official ARM design or started more or less from scratch.

[kragen]

Yeah, my understanding was that shipping a high-performance MIPS core with RISC-V instruction decoding was precisely their plan. It sounded like a pretty good plan, really. But did they manage to actually ship one? Did you get a look at a datasheet?

[monocasa]

No datasheet, but their commits to opensbi have been extremely enlightening wrt s and m modes.

[Findecanor]

I can only refer to MIPS' own press releases, unfortunately. They mention 4-wide OoO, RV64GH + Zbb + Zba. no V.

That is a frustrating pattern in the RISC-V world. Many companies that boast having x wide cores with y SPECint numbers but nothing that has been independently verified.

[kragen]

No V sounds like a bad sign for performance. Do they have any part numbers?

[hulitu]

> AFAIK MIPS still hasn't shipped a high-end processor competitive with the XuanTie 910 that article is about

The last high end MIPS was in the SGI times, 30 years ago.

[kragen]

Yes, but their claims over the last few years have been that their RISC-V implementations will be super fast, not like all those pikers, because they're using MIPS microarchitectural techniques. And so far I haven't seen them ship anything that substantiates that.

[chasil]

Loongson was making them until recently.

https://www.theregister.com/2025/05/06/loongson_inspur_cloud...

[kragen]

Yes, but MIPS wasn't.

[ajb]

It's an interesting comparison because MIPS used to occupy the niche that RV does now - an ISA that anyone could implement.

Lots of companies had their own mips implementation, but still might use an implementation from mips-the-company because even if you have your own team, you probably don't want to implement every core size that you might need. But then for some reason lots of them switched to using ARM, within a few years (in some cases getting an architecture licence and keeping their CPU team).

It seems like RV has a more stable structure, as the foundation doesn't licence cores, so even if one or two of the implementors die it won't necessarily reflect on the viability of the ecosystem

[bobmcnamara]

> an ISA that anyone could implement.

You want to burn your initial capital on lawyers? This is MIPS we're talking about.