Adding to what was said, it also suspiciously looks like a MIPS core with a RISC-V frontend strapped to it sort of like Qualcomm did with their Nuvia AArch64 core. Particularly stuff like the soft fill TLB from m-mode looks just like MIPS coprocessor 0.
There's nothing especially wrong with using an existing backend design and transitioning it to another ISA; a number of teams did that from mips->arm and had success with the result. Of course, if you ship too early you may be missing some features.
> a number of teams did that from mips->arm and had success with the result.
Do you have any examples? Apple Silicon cores took pieces of the pwerficient cores, and everything else I know of either tweaked an official ARM design or started more or less from scratch.
I don't know the details of how much rework they had to do.
As I understand it cavium still sells processors but only directly to hyperscalers.
Ironically Cavium may have gone through the same process with their previous design, but given that they then acquired this one from broadcom, perhaps it didn't go very well! I have no concrete information though.
Yeah, my understanding was that shipping a high-performance MIPS core with RISC-V instruction decoding was precisely their plan. It sounded like a pretty good plan, really. But did they manage to actually ship one? Did you get a look at a datasheet?
I can only refer to MIPS' own press releases, unfortunately. They mention 4-wide OoO, RV64GH + Zbb + Zba. no V.
That is a frustrating pattern in the RISC-V world. Many companies that boast having x wide cores with y SPECint numbers but nothing that has been independently verified.