[kragen]

Yeah, my understanding was that shipping a high-performance MIPS core with RISC-V instruction decoding was precisely their plan. It sounded like a pretty good plan, really. But did they manage to actually ship one? Did you get a look at a datasheet?

[monocasa]

No datasheet, but their commits to opensbi have been extremely enlightening wrt s and m modes.

[kragen]

Aha! I never would have thought to look there!