[ryao]

So far, patent lawsuits have been more of a problem for those using ARM designs (Qualcomm) than those using RISC-V designs. The Raspberry Pi foundation, Western Digital and Nvidia have successfully put RISC-V designs into their products without any issues. The first two even made their core designs open source (see Hazard3 and SweRV).

[fidotron]

How are SiFive going to protect their IP when everyone is free to copy it?

Patents.

[RetroTechie]

You're not free to copy SiFive's IP cores.

Open ISA != all implementations of it are free (although in RISC-V case, many are).

[fidotron]

Sorry, that was poorly worded.

My point is that if RISC-V takes off people will struggle to do decent implementations of it without stepping on the toes of the people already in the area.

I'd go so far as to say this is the entire SiFive strategy.

[ryao]

RISC-V already has taken off. There are billions of RISC-V cores shipped in consumer products every year. Adoption outside of the embedded MCU space is slower, but that is natural. Your FUD about SiFive is absurd. Hardware patents related to CPU design are typically ISA independent.

[fidotron]

> Hardware patents related to CPU design are typically ISA independent.

So that is merely the entire semiconductor industry patent portfolio that you will have to avoid.

[ryao]

That has not stopped new CPU designs from being made for any architecture and will not stop RISC-V designs from being made. If this were an actual problem, no one could design CPUs.

[ryao]

Anyone is free to make a RISC-V CPU without infringing on SiFive’s IP.

[fidotron]

Which in practice will mean free to make simplistic implementations using the lessons of twenty years ago.

If this was a winning strategy those open source implementations of SuperH cores would have been incredibly popular instead of dying in obscurity.

[ryao]

SuperH is owned by Hitachi. You cannot use them without a license from Hitachi as far as I know. RISC-V is unique in that its creator permits anyone to make and use RISC-V cores royalty free. It also supports 64-bit, which SuperH never did.

In any case, you should probably stop writing before you shove your foot any deeper into your mouth.

[fidotron]

https://j-core.org/

> In any case, you should probably stop writing before you shove your foot any deeper into your mouth.

Apology expected.

[ryao]

You should apologize to the people reading your comments for wasting their time. It is clear you are clueless about RISC-V and your foot is well into your mouth.

As for the J2, its creator does not request licensing fees, but Hitachi might require them. Unlike RISC-V, the creator of SuperH (Hitachi) is not known to have declared the ISA to be royalty free. I am not aware of such a declaration and even if there was, it is irrelevant because there is no reason to use SuperH over RISC-V. Nothing about the J2 supports the FUD you are spreading about RISC-V.

[camel-cdr]

Not so simplistic, see the XiangShan HotChips presentation:

https://hc2024.hotchips.org/assets/program/conference/day2/2...