[fidotron]

Sorry, that was poorly worded.

My point is that if RISC-V takes off people will struggle to do decent implementations of it without stepping on the toes of the people already in the area.

I'd go so far as to say this is the entire SiFive strategy.

[ryao]

RISC-V already has taken off. There are billions of RISC-V cores shipped in consumer products every year. Adoption outside of the embedded MCU space is slower, but that is natural. Your FUD about SiFive is absurd. Hardware patents related to CPU design are typically ISA independent.

[fidotron]

> Hardware patents related to CPU design are typically ISA independent.

So that is merely the entire semiconductor industry patent portfolio that you will have to avoid.

[ryao]

That has not stopped new CPU designs from being made for any architecture and will not stop RISC-V designs from being made. If this were an actual problem, no one could design CPUs.

[fidotron]

To quote you elsewhere in this thread:

> Patents tend to expire at different times around the world, plus there is the possibility of submarine patents. Without a declaration from Hitachi, adopting any processor design using their ISA is likely considered a legal risk.

If you combine this with your observation that CPU patents tend to be ISA independent then surely any widespread commercial deployment of RISC-V requires an assertion from everyone else in the semi industry that they do not in fact own patents on your implementation of it or it is likely considered a legal risk.

That or you just hold some things to different standards than others.

[ryao]

There is a history of industry litigation over people implementing others’ ISAs without their full blessing. The Qualcomm ARM lawsuit was the most recent example of this. There is less litigation over people designing CPUs using ISAs whose designers permitted reuse.

You keep trying to spread FUD concerning RISC-V. The issue you are trying to raise is one that if valid, would prevent anyone from designing a CPU, yet many do without legal issues. Hence, the issue you raise is invalid (by modus tollens).