[KenoFischer]

My understanding is that the TinyTapeout people were using efabless as a service provider and efabless was also providing some sponsorship, but that they are institutionally distinct. There's a LinkedIn post from the TinyTapeout folks that they're looking into alternatives.

[kragen]

That's a relief! And Tiny Tapeout has already done a beta with IHP's open-source 130nm BiCMOS SiGe PDK.

The IHP PDK is really a lot more exciting to me than the Skywater stuff because it's aimed at submillimeter analog things (450GHz fₜ, 650GHz fastest oscillator) and why would you fab a digital design in 130nm instead of just programming an FPGA?

[le-mark]

> why would you fab a digital design in 130nm instead of just programming an FPGA?

That’s an interesting concept. So an fpga implemented on a current 7nm process is more performant (clock speed and energy use) than an asic on a 130nm process? How about 40nm process? I feel like there’s a graph of intersecting lines here.

[pclmulqdq]

I think perf is usually relatively close between an optimized design in a 7 nm FPGA and an optimized design in ~40 nm CMOS, but it's not 1:1. The FPGAs are usually higher-performance than 130 nm, but there are certain things that are easier in ASICs (eg analog-related stuff).

[comex]

Speaking as a newbie - FPGAs can't get anywhere near the same clock speed, though, right? So the equivalence only applies if the work is parallelizable?

[pclmulqdq]

With the exception of the highest clock speed chips (eg Intel CPUs), clock speeds can actually be comparable. 45 nm CPUs got to 2.5 GHz, and if you tickle a 7 nm FPGA just right it can get to ~800 MHz to a GHz. Things like microcontrollers and chips that are generally less optimized than the old Intel CPUs (which were mostly drawn at the transistor level and use a speed-optimized process) are much closer in speed. A 3-stage RISC-V at 45 nm is probably also running at 400 MHz or less, and the FPGA is capable of a 3 stage RISC-V at that speed.

But yes, in general, FPGAs on certain computational tasks will need deeper pipelines or the use of parallelism. Usually, pipeline depth works. Actually, if you look at the Intel front side bus (less optimized than the core), that's about the speed you can get from a 7 nm FPGA.

[nickelpro]

The Sky130 IO pads can't go faster than 33Mhz (at least the ones in the open source PDK), and the OpenLane flow isn't yet timing driven, so anything internal isn't going to break more than 100Mhz. These aren't fast chips or fast processes, Skywater is mostly for pedagogical and niche military and research tapeouts.

[genewitch]

$4600 on ebay for a 7/10nm xilinx versal. So is 130nm/40nm ASIC cheaper than $4600?

[pclmulqdq]

A few sq mm at 40 nm is about $20k, and you can only configure it once. I think the Versal also gives you more useful gates at that size (thanks to block RAMs and hard multipliers).

[throwaway81523]

What about power consumption?

[pclmulqdq]

The FPGA will have higher static power (running all the overheads) but probably lower dynamic power for the same design. 40 nm is old at this point for high-performance chips.

[throwaway3572]

That price is probably $4600 for one Xilinx Versal.

For the MPW run you would get ~100 parts. When everything is said and done, and you pay for packaging etc., on a MPW run you'll likely pay something like $50K. So ~$500ea

The eFabless price of $10K for a full run, including a packaged part, was an unparalleled deal.

[imtringued]

https://www.digikey.de/en/product-highlight/e/efinix/titaniu...

Ok it's 14nm. Who cares.

[15155]

This is a single chip. At scale, the ASIC is absolutely cheaper.

[willis936]

Radiation tolerance is one case. For the price of a tiny tapeout run you could count on one hand how many qualified radiation tolerant ICs you could buy. There's some sauce involved with process choices for radiation tolerance, but one of critical things to do is use large features.

[bgnn]

IHP is excitinybut their PDK is horrible compared to major fabs like TSMC or GF. Anyone using it for products hate it.

[kragen]

Hmm, that's interesting. What are the major pain points? As you can probably guess, I don't have access to TSMC's or GF's PDKs.

[bgnn]

Inaccuracies with respect to the silicon (active and passove parsitics, mechanical stress effects, temperature dependencies etc) mainly, user friendliness and proper documentation as secondary .

[kragen]

Thank you!

[15155]

> and why would you fab a digital design in 130nm instead of just programming an FPGA?

Because you need some analog features with your digital design.

[kragen]

If you need some analog features, that's conventionally called a "mixed-signal design", not a "digital design". I wasn't talking about mixed-signal designs, for which it's obvious that an FPGA is unlikely to work.

[nickpsecurity]

You should really look into summaries on how deep sub-micron adds more problems as processes shrink. It's crazy that 28nm and under even work at all. They also break faster in more ways than larger, mature nodes.

Far as 130nm, I'll give you a few reasons I'd use one over a 7nm FPGA. This is a non-HW guy saying what he's heard from pro's at different times. HW people, feel free to correct me about whatever I get wrong.

1. Unit prices. If you can take the upfront cost (NRE), the per unit price will be much lower than FPGA's. You might charge plenty per unit depending on the market. This can be a source of profit.

2. Older, larger nodes are said to be better for analog. Lots of designs are mixed-signal to use analog for it's lower power, extra performance, or how it doesn't blink (no rise/fall with clock).

3. ASIC's can't be reprogrammed like FPGA's. The custom design might be more secure like Sandia Secure Processor (Score) or CHERI RISC-V. FPGA's can only do one of these except for antifuse FPGA's.

4. Larger nodes are easier to visually inspect for backdoor with cheaper, teardown hardware. Who knows what's in the FPGA's.

5. Larger nodes are easier to synthesize, P&R, and auto-inspect (eg Calibre). That means open-source tools have a better chance of working or even being developed.

6. If not too power hungry (or power is cheap), some applications can let you outperform 7nm parts with parallel use of 130nm parts which are much cheaper or highly-optimized. An example what media wanting to do distributed, massively-parallel design for doing NN training maybe with 8-bitters and on-board, analog accelerators. My inspiration, aside from old MPP clusters (eg Thinking Machines), was a wafer-scale, analog NN done before Cerebras.

7. Improved reliability in general. In trusted checkers or fault-tolerant configuration, I feel like the 130nm parts are less likely to have a double failure or fail before the 7nm nodes.

8. If there's a business case, saying you built your own hardware is cool. It might even attract talent who benefit the company in other ways.

That's off the top of my head. Again, I just read a lot of stuff on ASIC's.

On a side note, you might find eASIC's Nextreme's interesting. They're Structured ASIC's that work like FPGA's in that design gets put on something with pre-made blocks to save money. Except, instead of software programmed, some via or metal layers get customized for the routing. While that reduces NRE cost, doing the routing in hardware supposedly reduces unit prices and energy maybe with a performance boost. They used to sample chips out quickly and relatively cheaply. Also, I think Triad Semiconductor had S-ASIC's with analog stuff.

[kmeisthax]

eASIC Nextreme sounds like a good ol' fashioned ULA (uncommitted logic array), the sort of thing that's at least as old as the Sinclair ZX81 (where it drove the per-unit cost through the floor).

[nickpsecurity]

I hadn't heard of that. Looking it up, it's a type of gate array which I believe inspired both S-ASIC's and devices like FPGA's. Here's an intro to each for those following along:

https://en.m.wikipedia.org/wiki/Gate_array

http://eda.ee.ucla.edu/EE201A-04Spring/ASICslides.ppt

I also found a link with the pricing of one. It was $45,000 for 45 prototypes on 45nm through eASIC.

https://www.design-reuse.com/news/25107/easic-45nm-asic-valu...

That put having chips made into the realm of possibilities for even a small business. Other costs might prevent that but I could see more stuff opening up. I also envisioned hard blocks done on those nodes for common components so the S-ASIC was used for custom logic (eg differentiators).

[kragen]

Thanks! Yeah, for analog the case is obvious, both because there's no such thing as an analog FPGA and because smaller feature size comes with big drawbacks for analog; that's why I said, "why would you fab a digital design in 130nm". The others I'm less sure about, but they do sound plausible.

[nickpsecurity]

One more gift for you, buddy.

https://en.m.wikipedia.org/wiki/Field-programmable_analog_ar...

https://www.anadigm.com/fpaa.asp

https://hasler.ece.gatech.edu/FPAA_IEEEXPlore_2020.pdf

[kragen]

Yeah, there have been a dozen different attempts to make "an FPGA, but analog". This is one of them. They all failed. You'll note the page hasn't been updated since 02006: https://web.archive.org/web/20060715013941/http://www.anadig.... Analog circuits aren't fungible the way digital circuits are.

I'm not saying it's not a worthwhile research direction, just that it hasn't borne commercially viable fruit so far, despite decades of attempts.

[genewitch]

wait, does 130nm imply i can send them verilog and receive ASICs in the mail?

[kragen]

Basically yes, but you have to generate the GDS-II from your Verilog yourself, you have to pay them several thousand dollars, the turnaround time is nearly a year, and your first and maybe second and third tapeout will probably have bugs that keep it from working at all.

[genewitch]

This comports with my - admittedly decade-and-a-half old - understanding of the code to silicon pipeline/flow.

[Joel_Mckay]

There are open tool chains that will compile your design using the cells defined in the outreach programs fab specific standards. However, it will not necessarily function like your simulated hardware design.

Getting the hardware cell simulation working is not trivial, and Synopsys charges more per seat than most startups spend on labor in a year.

YMMV =3