[pclmulqdq]

I think perf is usually relatively close between an optimized design in a 7 nm FPGA and an optimized design in ~40 nm CMOS, but it's not 1:1. The FPGAs are usually higher-performance than 130 nm, but there are certain things that are easier in ASICs (eg analog-related stuff).

[comex]

Speaking as a newbie - FPGAs can't get anywhere near the same clock speed, though, right? So the equivalence only applies if the work is parallelizable?

[pclmulqdq]

With the exception of the highest clock speed chips (eg Intel CPUs), clock speeds can actually be comparable. 45 nm CPUs got to 2.5 GHz, and if you tickle a 7 nm FPGA just right it can get to ~800 MHz to a GHz. Things like microcontrollers and chips that are generally less optimized than the old Intel CPUs (which were mostly drawn at the transistor level and use a speed-optimized process) are much closer in speed. A 3-stage RISC-V at 45 nm is probably also running at 400 MHz or less, and the FPGA is capable of a 3 stage RISC-V at that speed.

But yes, in general, FPGAs on certain computational tasks will need deeper pipelines or the use of parallelism. Usually, pipeline depth works. Actually, if you look at the Intel front side bus (less optimized than the core), that's about the speed you can get from a 7 nm FPGA.

[nickelpro]

The Sky130 IO pads can't go faster than 33Mhz (at least the ones in the open source PDK), and the OpenLane flow isn't yet timing driven, so anything internal isn't going to break more than 100Mhz. These aren't fast chips or fast processes, Skywater is mostly for pedagogical and niche military and research tapeouts.