[le-mark]

> why would you fab a digital design in 130nm instead of just programming an FPGA?

That’s an interesting concept. So an fpga implemented on a current 7nm process is more performant (clock speed and energy use) than an asic on a 130nm process? How about 40nm process? I feel like there’s a graph of intersecting lines here.

[pclmulqdq]

I think perf is usually relatively close between an optimized design in a 7 nm FPGA and an optimized design in ~40 nm CMOS, but it's not 1:1. The FPGAs are usually higher-performance than 130 nm, but there are certain things that are easier in ASICs (eg analog-related stuff).

[comex]

Speaking as a newbie - FPGAs can't get anywhere near the same clock speed, though, right? So the equivalence only applies if the work is parallelizable?

[pclmulqdq]

With the exception of the highest clock speed chips (eg Intel CPUs), clock speeds can actually be comparable. 45 nm CPUs got to 2.5 GHz, and if you tickle a 7 nm FPGA just right it can get to ~800 MHz to a GHz. Things like microcontrollers and chips that are generally less optimized than the old Intel CPUs (which were mostly drawn at the transistor level and use a speed-optimized process) are much closer in speed. A 3-stage RISC-V at 45 nm is probably also running at 400 MHz or less, and the FPGA is capable of a 3 stage RISC-V at that speed.

But yes, in general, FPGAs on certain computational tasks will need deeper pipelines or the use of parallelism. Usually, pipeline depth works. Actually, if you look at the Intel front side bus (less optimized than the core), that's about the speed you can get from a 7 nm FPGA.

[nickelpro]

The Sky130 IO pads can't go faster than 33Mhz (at least the ones in the open source PDK), and the OpenLane flow isn't yet timing driven, so anything internal isn't going to break more than 100Mhz. These aren't fast chips or fast processes, Skywater is mostly for pedagogical and niche military and research tapeouts.

[genewitch]

$4600 on ebay for a 7/10nm xilinx versal. So is 130nm/40nm ASIC cheaper than $4600?

[pclmulqdq]

A few sq mm at 40 nm is about $20k, and you can only configure it once. I think the Versal also gives you more useful gates at that size (thanks to block RAMs and hard multipliers).

[throwaway81523]

What about power consumption?

[pclmulqdq]

The FPGA will have higher static power (running all the overheads) but probably lower dynamic power for the same design. 40 nm is old at this point for high-performance chips.

[kragen]

The static power might also depend on whether the FPGA is an SRAM type or a floating-gate type, I'd think. Does Lattice have any parts fabbed in relatively new processes?

[pclmulqdq]

You're right. Pretty much everything is SRAM now, though. Even the MAX 10 is an SRAM FPGA with a flash-backed storage memory.

[throwaway3572]

That price is probably $4600 for one Xilinx Versal.

For the MPW run you would get ~100 parts. When everything is said and done, and you pay for packaging etc., on a MPW run you'll likely pay something like $50K. So ~$500ea

The eFabless price of $10K for a full run, including a packaged part, was an unparalleled deal.

[imtringued]

https://www.digikey.de/en/product-highlight/e/efinix/titaniu...

Ok it's 14nm. Who cares.

[15155]

This is a single chip. At scale, the ASIC is absolutely cheaper.