[thrtythreeforty]

My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part.

This may be the first HDL I've seen that attempts to move the needle on catching bugs at compile time. (I've worked with several engineers, on hardware bugs which turned out to be pipelining errors, who did not understand what I meant by "make this design error inexpressible.") I have several pages of notes on what I'd do differently if I designed my own HDL - the typical software engineer hubris - and this is the first language I've seen that starts to line up with what I was thinking.

Another perennial area where bugs crop up are when crossing clock and reset domains. The language ought to be able to make it so that you simply can't make many kinds of clock domain errors - trying to read a signal from the wrong clock domain shouldn't compile. Dedicated "unsafe" primitives from a stdlib should perform the crossing and the type conversion.

[FPGAhacker]

Every time I see one of these pop up, the thought that software engineers are forever trying to avoid knowledge, understanding, and wisdom with another layer of abstraction comes to mind.

I’m all in favor of a better HDL. Verizon/SystemVerilog is loaded with completely non-obvious landmines. I’ve been doing this so long I forget they are there, but it’s pretty painful seeing someone new to the language step on them. But the alternative, VHDL has largely fallen out of favor in the US.

You would be hard pressed to find a more strongly typed language than VHDL, but damn is it verbose. None of the footguns, but you might get an RSA before you finish typing the code in. If you have ever given Ada a try, VHDL will look pretty familiar.

I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks.

Done without discipline you will spend all your time debugging. Wondering why it worked in the lab an hour ago, but after lunch nothing works and you won’t be able to make sense of it.

Understanding basic combinational logic, then sequential logic, followed by state machines (which are the bread and butter of digital design), followed by understanding IO timing and timing constraints (a brain damaged “language” to itself) will take you far.

Domain crossing isn’t so bad if you have those fundamentals.

Then you can spend time learning algorithms other more interesting things. Writing low power software accelerators for neural nets and signal processing.

You can go through all the gyrations of language design in the world, but the language isn’t the hard part. There is a huge amount of improvement to be done, no doubt. But digital design is not the language.

If you want to make the world of digital design a better place, more open, easier to break into, work on tools, not languages. I’d give a kidney for an open source timing diagrammer that could do simple setup and hold checks, create derived signals through Boolean combinations of other signals, and emulate a flop.

I’d do it, but I’ve tried and programming a gui is about the most painful thing I’ve done on a computer. So much work for so little payoff.

[rowanG077]

> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks.

I say this as an FPGA engineer that started my career in software: This used to be the case in software too. But we now have such good tools with REPLs, automatic tests, IDE integrations, partial implementation possibility that it's simply way less inefficient to build software like that.

I feel like that is precisely where the current hardware ecosystem stands. VHDL/Verilog/SV are simply not good enough to use it as a design exploration tool.

Instead of saying: "We use HDLs just to put in the design which we do beforehand" it should be "HDLs are the central tool in digital design. Both during design exploration and implementation". I think this is what people want out of these "neo" HDLs. The way you are viewing it is as only as a straightforward drop-in replacement. That is not what it's about.

[nsteel]

> during design exploration and implementation"

Assuming you meant to also include 'verification', then I can agree somewhat.

As an ASIC designer, you usually get just one stab at a hardware implementation, there's no 0-day point release. It's got to work so you spend the minimum time typing it in. Then you devote the maximum time to verifying it. I think some of the very poor quality s/w we are all subject to is partly due to a false sense of security that sw tooling provides. I expect fully working and efficient hardware, I'd like that from my software too, but in reality I rarely get that. The idea of applying more software dev processes/principles to hardware is a bit frightening to me.

[rowanG077]

Not all circuit design is asic. There is a ton of FPGA work. But in general I do agree with you. The move fast and break things ethos is something you shouldn't really import ;).

[zozbot234]

> Assuming you meant to also include 'verification', then I can agree somewhat.

This project involves static verification of one part of hardware design, namely the timing properties of pipelines and sequential circuits.

This is not all of verification (which is a huge issue in modern semiconductor design) or even of high-level design verification, but it probably helps.

[thezoq2]

I'm also an FPGA person that started off in software and this is exactly how I feel, and the reason I'm building my own HDL too. Software languages have evolved so much since the 80s and are so much more productive, HDLs have missed out on that, but convincing hardware engineers about that is an uphill battle

[nxobject]

Hell, I'd even give my left nut for a vendor- and IDE-agnostic tool that would convert a schematic to your HDL of choice. I still do a lot of work on graph paper.

[artemonster]

„they“ (someone not working in the field) try to solve a problem (i.e. warts in old and mature languages) that is literally not a problem in the field at all. Then they get pissed at you when you point it out that nobody needs this, like at all. Oh well.

[incrudible]

It works the other way around too, hardware getting designed that no sofware person asked for or wants to develop for. Most hardware people are bad at software design, and vice versa, but the differences are necessarily papered over in software, leaving a lot of the theoretical gains on the table.

[actionfromafar]

But couldn't there be languages where it was easier to express that design? Your description reminds me what it's like to program in C.

[thezoq2]

I love how this is being downvoted! Writing Verilog or VHDL is exactly like writing C, or maybe even assembly

[gchadwick]

> My experience with most "neo HDLs" is that they are all code generators which make the tedious part easy and don't really end up touching the hard part.

That's generally make take too, only I'd say they make some of the hard parts harder.

When you're getting into timing, power and area optimizations it's important to have a good mental mapping from the HDL you're writing to the circuitry (or FPGA configuration) being produced. For some optimizations you also need to smash through neat abstractions.

Often these new HDLs abstract away more from the circuitry so you have to carry more things in your head to think through these optimizations. They aim to work out the details for you but those details matter and when you only have indirect control over them can make things more difficult.

In software we're generally happy to accept a drop in performance or an increase in memory usage to gain powerful abstractions and increase developer productivity. In hardware this is often less acceptable (in particular if you're building high-performance CPU, GPU, AI accelerators etc).

From my brief look at the front page of the Filament website I do like the type system but from experience building real CPUs (I worked on the A55, A510 and E1 at arm, focussed on memory systems and now work on Ibex: https://github.com/lowrisc/ibex amongst other things) bugs and other issues around pipelining are often to do with stall conditions, I wonder how well it can handle that? Stall conditions were large and complex and also where you had to do lots of those abstraction busting optimisations to meet timing so it's critical you have a strong grasp of the critical paths being produced in the circuitry. My fear with Filament is it abstracts a bunch of that away.

Of course the entire hardware world isn't CPUs, there could well be areas of design this kind of language works well. In particular I can see it's useful for prototyping/design exploration type work.

[Brian_K_White]

I think I don't understand how to make a design error inexpressible either.

I know what the statement means, but I fail to imagine any hardware construction that is automatically wrong, merely ones that don't do what someone wanted. The same exact construct and resulting behavior could be what someone else wanted.

Violating the nominal specs, or the nominal intended purpose of a part or circuit to get particular results is the oldest thing in the world.

Maybe some things are common enough that it's reasonable to make them difficult to express?

Ok, also especially if you can assert your intentions with labels that say high level things, then I guess I can see being able to flag some things that would break the intentions expressed by the labels.

Maybe I'm starting to imagine a little.

[hgomersall]

We use the python based myhdl extensively and are very successful in writing hdl for fpga that has vanishingly few bugs. The reason why myhdl makes this possible is that testing is relatively trivial, so we use it properly (i.e. everywhere). You're right that it doesn't solve the hard problem, and discipline is needed around things like clocks, but it does enable modern development techniques and when writing RTL, HDL is very amenable to extensive tests to quash bugs.

[incrudible]

I am always suspicious about entrenched people claiming that this or that is not the hard part. Maybe that is true, but it can still be tedious or error prone, and this is most obvious to someone who is still bothered by it, whereas the old guard is already numb to it.