[nsteel]

> during design exploration and implementation"

Assuming you meant to also include 'verification', then I can agree somewhat.

As an ASIC designer, you usually get just one stab at a hardware implementation, there's no 0-day point release. It's got to work so you spend the minimum time typing it in. Then you devote the maximum time to verifying it. I think some of the very poor quality s/w we are all subject to is partly due to a false sense of security that sw tooling provides. I expect fully working and efficient hardware, I'd like that from my software too, but in reality I rarely get that. The idea of applying more software dev processes/principles to hardware is a bit frightening to me.

[rowanG077]

Not all circuit design is asic. There is a ton of FPGA work. But in general I do agree with you. The move fast and break things ethos is something you shouldn't really import ;).

[zozbot234]

> Assuming you meant to also include 'verification', then I can agree somewhat.

This project involves static verification of one part of hardware design, namely the timing properties of pipelines and sequential circuits.

This is not all of verification (which is a huge issue in modern semiconductor design) or even of high-level design verification, but it probably helps.