[rowanG077]

> I know this may be a weird thing for software folks to think about, but writing HDL is a tiny part of digital design. In digital design, if done with discipline, writing the HDL is an almost mechanical process of translating the design. In a design that might take a year, writing the code might be 3 weeks.

I say this as an FPGA engineer that started my career in software: This used to be the case in software too. But we now have such good tools with REPLs, automatic tests, IDE integrations, partial implementation possibility that it's simply way less inefficient to build software like that.

I feel like that is precisely where the current hardware ecosystem stands. VHDL/Verilog/SV are simply not good enough to use it as a design exploration tool.

Instead of saying: "We use HDLs just to put in the design which we do beforehand" it should be "HDLs are the central tool in digital design. Both during design exploration and implementation". I think this is what people want out of these "neo" HDLs. The way you are viewing it is as only as a straightforward drop-in replacement. That is not what it's about.

[nsteel]

> during design exploration and implementation"

Assuming you meant to also include 'verification', then I can agree somewhat.

As an ASIC designer, you usually get just one stab at a hardware implementation, there's no 0-day point release. It's got to work so you spend the minimum time typing it in. Then you devote the maximum time to verifying it. I think some of the very poor quality s/w we are all subject to is partly due to a false sense of security that sw tooling provides. I expect fully working and efficient hardware, I'd like that from my software too, but in reality I rarely get that. The idea of applying more software dev processes/principles to hardware is a bit frightening to me.

[rowanG077]

Not all circuit design is asic. There is a ton of FPGA work. But in general I do agree with you. The move fast and break things ethos is something you shouldn't really import ;).

[zozbot234]

> Assuming you meant to also include 'verification', then I can agree somewhat.

This project involves static verification of one part of hardware design, namely the timing properties of pipelines and sequential circuits.

This is not all of verification (which is a huge issue in modern semiconductor design) or even of high-level design verification, but it probably helps.

[thezoq2]

I'm also an FPGA person that started off in software and this is exactly how I feel, and the reason I'm building my own HDL too. Software languages have evolved so much since the 80s and are so much more productive, HDLs have missed out on that, but convincing hardware engineers about that is an uphill battle