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by alted
1210 days ago
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Judging from [1], Sam Zeloof's plan might include using electron beam lithography, which scans an electron beam over a wafer surface, instead of normal photolithography. This can get high resolution (10nm) comparable with EUV, and could theoretically be built out of a hacked scanning electron microscope. Photolithography is the step that limits fabrication size, so e-beam litho allows cheap transistors comparable with state-of-the-art. The main problem is e-beam litho is extremely slow. It might take ~1 day to do a single photolithography step for a 1x1cm chip, whereas an EUV machine can pattern a 300mm diameter silicon wafer in < 1 minute. (The next problem is making everything reliable. Billions of transistors (a modern CPU) needs a failure rate per transistor of better than 1e-9.) Maybe that's enough for extremely-low-volume production? [1] https://mobile.twitter.com/szeloof/status/154993704406717235... |
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[1] https://nl.wikipedia.org/wiki/Mapper_Lithography (no English page available)
[2] https://www.asml.com/en/news/press-releases/2019/asml-agrees...