[sylware]

Well, the video does not show the ppl actually designing the blueprint of the machine and doing the R&D, the real brains... we are showed mostly assembly workers (all above averagely skilled), customer service operators, etc.

I was surprised to agree with most of what ASML bosses said, and I would have given exactly the same answer than the assembly operator, namely not providing any timeline... because it is complete garbage to do so on so much complex machines, not to mention the machine is a prototype, then the first one. I may have answered "yesterday".

But noway they will make me use a doz computer, or an android phone...

I am _seriously_ curious on how they want to get their pitch below 7nm with a 13.6nm EUV light. Do they plan to go massive multi-patterning with sub-nm xray positioning? For below 7nm pitch, what would they use: xray light? electron/ion beams? pattern printing? And what about the purity of the wafer dopped silicon for smaller features? xray light: what materials to use?? Quantum interference tricks?

I wonder how many silicon atoms from a wafer crystal we have on a 1nm row...

All that is to get chips which consume less energy, get faster telecom, play magnificient games, store more in flash ram.

[adrian_b]

The so-called "5 nm" CMOS processes have minimum pitches around 30 nm.

I do not know what minimum pitches are planned for the future so-called "2 nm" CMOS processes, but it is likely that they would not be smaller than 15 to 20 nm.

So there will be some time until multiple patterning could be needed again, and by that time there are chances that the transistors will have minimum sizes determined by other causes than lithography, so for further progress a switch to different semiconductor materials will be needed, not a further improvement of lithography.

[MayeulC]

Gate length is already determined by tunneling current, you can't really go below 20 nm on Si. Width is determined by the current density you want, and can be reduced with better electrostatic control (FDSOI, FinFET, GAA...)

[sylware]

EUV High NA can "draw" 7nm features, with heavy design constraints and alignment equipment, they can sort of go "below", but even with new electrostatic transistor design, they are sort of limited at 20nm for the gate lenght?

Then the litographer does not seem to be the limiting equipment anymore. I guess there is heavy R&D going into electrostatic transistor design and crystals to deal with the gate current below 20nm.

I wonder at which size, silicium doping does not work "enough" anymore.

[MayeulC]

At some point the electons start tunneling through the channel, regardless of its state... I don't remember my semiconductor theory that well, but possibly unaffected by the height of the potential barrier? In which case better electrostatic control or changing materials does nothing. Hot carriers (high voltages) are more affected, so you can lower voltages to an extent.

You can go below 20 nm, but you get this constant tunneling current, which deteriorates your on/off ratio, and increases power consumption (and TDP). It's doable if you can turn that part of the die off (dark silicon).

[sylware]

Alright, then if they manage to handle properly this tunneling current in order to get clean on/off, they still will be able to shrink the current transistor feature size... which is actually huge if we don't think about the marketing "Xnm lie", unless another limiting factor hits.

In the silicon crystal lattice, without considering "doping", the atomic valence lenght is 2.35 angstrom or 0.254 nm, and unit lenght 5.44 angstrom or 0.544 nm.

So a feature of 7nm is hardly 14 silicon crystal lattice units. With doping, I wonder if it will be ever required to have a better pitch to have something to work with silicon, unless near "atomic perfect" doping in near "atomic perfect" silicon crystals can still be used for on/off gates.

It makes me pessimistic on the amount of remaining transistor shrink steps. "2nm" maybe "1nm" then you would need to assemble atom per atom perfect lattices frozen in time.

[mike_hearn]

The documentary spends a lot of time interviewing their head of R&D who is described as the 'mad professor', he talks extensively about the problem of the tin exploding onto the mirror and how he encountered that problem etc, so presumably he should count as someone doing R&D for real.

[sylware]

The head of R&D, but he is the only "real brain" who is presented on the show. Could have presented maybe 1 other "real brain".

I have heard about "the 2 times lazered tin droplet to generate "enough" EUV light" already in an older ASML documentary (years ago).

[hnuser123456]

If I understand correctly, chips down to 14nm were made using ~190nm light, not sure how that worked but if that ratio of 10x+ holds, seems like 1nm fab using 13nm light should be doable with the same techniques, not to mention improved ones?

[sylware]

Idem, if I understand correctly, to go below the light pitch with DUV litographers, multi-patterning had to be used: a huge burden at chip design time and "pressure" on nm-grade alignment equipment (heard about coupled piezo electric motors with xray interferometers?), which is supposed to be from Taiwan.

In other words: photomask madness.

Photomask manufacturing is another critical part of silicium chip manufacturing. It seems EUV photomask are special (no more transparent crystals, but instead reflective "patterned" surfaces?), wonder if they are still using electron/ion beams to engrave patterns.

Wonder where are manufactured EUV photomasks, heard about Japan a lot.

Oh, and I realised that I am really curious on how they keep the EUV mirrors clean from the tin droplets :) Wild guess: EUV mirrors far away, H2 gas reaction, etc?).

[MayeulC]

7nm feature size or process? 7nm processes are on ~20 nm feature sizes, but have tighter alignment constraints, as they move into the 3D world.