[adrian_b]

The so-called "5 nm" CMOS processes have minimum pitches around 30 nm.

I do not know what minimum pitches are planned for the future so-called "2 nm" CMOS processes, but it is likely that they would not be smaller than 15 to 20 nm.

So there will be some time until multiple patterning could be needed again, and by that time there are chances that the transistors will have minimum sizes determined by other causes than lithography, so for further progress a switch to different semiconductor materials will be needed, not a further improvement of lithography.

[MayeulC]

Gate length is already determined by tunneling current, you can't really go below 20 nm on Si. Width is determined by the current density you want, and can be reduced with better electrostatic control (FDSOI, FinFET, GAA...)

[sylware]

EUV High NA can "draw" 7nm features, with heavy design constraints and alignment equipment, they can sort of go "below", but even with new electrostatic transistor design, they are sort of limited at 20nm for the gate lenght?

Then the litographer does not seem to be the limiting equipment anymore. I guess there is heavy R&D going into electrostatic transistor design and crystals to deal with the gate current below 20nm.

I wonder at which size, silicium doping does not work "enough" anymore.

[MayeulC]

At some point the electons start tunneling through the channel, regardless of its state... I don't remember my semiconductor theory that well, but possibly unaffected by the height of the potential barrier? In which case better electrostatic control or changing materials does nothing. Hot carriers (high voltages) are more affected, so you can lower voltages to an extent.

You can go below 20 nm, but you get this constant tunneling current, which deteriorates your on/off ratio, and increases power consumption (and TDP). It's doable if you can turn that part of the die off (dark silicon).

[sylware]

Alright, then if they manage to handle properly this tunneling current in order to get clean on/off, they still will be able to shrink the current transistor feature size... which is actually huge if we don't think about the marketing "Xnm lie", unless another limiting factor hits.

In the silicon crystal lattice, without considering "doping", the atomic valence lenght is 2.35 angstrom or 0.254 nm, and unit lenght 5.44 angstrom or 0.544 nm.

So a feature of 7nm is hardly 14 silicon crystal lattice units. With doping, I wonder if it will be ever required to have a better pitch to have something to work with silicon, unless near "atomic perfect" doping in near "atomic perfect" silicon crystals can still be used for on/off gates.

It makes me pessimistic on the amount of remaining transistor shrink steps. "2nm" maybe "1nm" then you would need to assemble atom per atom perfect lattices frozen in time.