[rpiguyshy]

maybe a stupid question but it wasnt clear to me how this is able to work when the system clock doesnt run fast enough to keep up with 60hz. i was wishing that there was more elaboration about what a PLL is and how it allows a person to get free clock cycles.

[WillFlux]

PLLs are common to many electronics system, if you’re looking for a primer, try https://www.analog.com/en/analog-dialogue/articles/phase-loc...

However, from the point of view of these designs, the PLL is an internal black box that allows us to generate an (almost) arbitrary clock frequency.

We choose a frequency to meet I/O or performance requirements. In this case a pixel clock of ~25 MHz: we have to meet this to generate a valid 640x480 video signal.

None of the Exploring FPGA Graphics designs uses a CPU: the logic is all in hardware, often a finite state machine. The trick is ensuring the hardware logic completes within one clock cycle. For 25MHz, each clock cycle is 40ns. If a design is too complex to meet timing, we can break it into multiple steps, similar to pipelining on a CPU[1].

You can also run different parts of a design at different clock frequencies, but this introduces the challenge of clock domain crossing[2].

For a low-end FPGA, like an Artix-7, you can expect to run a reasonably complex design at 100-200 MHz.

[1] https://en.wikipedia.org/wiki/Classic_RISC_pipeline

[2] https://en.wikipedia.org/wiki/Clock_domain_crossing

[pjc50]

PLLs ("phase locked loop") are entirely normal in both FPGA and microcontroller worlds. They involve a high-frequency oscillator and a frequency divider. The fast clock is divided down, as is the fast one, and the two signals compared. When they are out of phase, one is ahead of the other, and the fast oscillator adjusted accordingly.

This is also how PC BIOSes let you configure various CPU and DRAM speeds from a single physical crystal.

They're accurate enough for most practical purposes. They can take a large number of clock cycles to acquire "lock" and start producing the correct frequency, which rarely matters unless you need to go from 0 to X00MHz very quickly.

> system clock doesnt run fast enough to keep up with 60hz

It doesn't actually say that as far as I can tell?

[gugagore]

This is likely not a useful explanation if you do not specifically know what a a Phase-Locked Loop is, but I want to say that it is yet another example of how negative feedback can give you an implementation for the inverse of a component.

In this instantiation of the concept, a frequency divider (dividing by a whole number) is something that's easy to build: it's a counter. For example, to divide by 100, count the input clock, when you increment from 49, wrap around to 0, and toggle the output.

Putting that divider in a negative feedback loop gives you a multiplier.

Another common instantiation: if you put a voltage divider (easy to build with a couple of resistors) in the feedback path of an operational amplifier and you get a voltage multiplier.

Another instantiation with op-amps: Put a capacitor in the feedback path, and you "get" an inductor. This one is also a big deal because, practically speaking, it's easier to engineer close-to-ideal capacitors than it is inductors, which are heavy and lossy.

And if you really want to take a ride on this conceptual train, consider that it's easy to square a number. Need the square root? Use negative feedback: https://en.wikipedia.org/wiki/Newton%27s_method#Square_root

[liaukovv]

The problem with clocks is not how to generate them fast enough, but rather how to keep them exact and consistent

Phase locked loop can use reference clock(generated outside of the chip by an oscillating crystal, like in a watch) to generate many other clocks of different frequencies each of which is corrected and guided by this reference clock

In fpga there is no "system clock", each module can use its own clock at frequency that it needs, all defined and routed by the designer