[liaukovv]

The problem with clocks is not how to generate them fast enough, but rather how to keep them exact and consistent

Phase locked loop can use reference clock(generated outside of the chip by an oscillating crystal, like in a watch) to generate many other clocks of different frequencies each of which is corrected and guided by this reference clock

In fpga there is no "system clock", each module can use its own clock at frequency that it needs, all defined and routed by the designer