[pjc50]

PLLs ("phase locked loop") are entirely normal in both FPGA and microcontroller worlds. They involve a high-frequency oscillator and a frequency divider. The fast clock is divided down, as is the fast one, and the two signals compared. When they are out of phase, one is ahead of the other, and the fast oscillator adjusted accordingly.

This is also how PC BIOSes let you configure various CPU and DRAM speeds from a single physical crystal.

They're accurate enough for most practical purposes. They can take a large number of clock cycles to acquire "lock" and start producing the correct frequency, which rarely matters unless you need to go from 0 to X00MHz very quickly.

> system clock doesnt run fast enough to keep up with 60hz

It doesn't actually say that as far as I can tell?