[daeken]

> Having transistors closer together can also help overcome speed-of-light delay. This can be important in caches.

But in this case, while they take up less space, the distance is the same -- they're simply traveling up and over, rather than just over. Unless I'm missing something here.

[Symmetry]

The number of things of a given size you can fit on a plane within distance R of you is proportional to R^2. The number of things you can fit in a three dimensional space is R^3. So as we utilize 3D more and more things will tend to be closer together.

[daeken]

They're closer together, but the distance traveled in total is the same. Imagine the transistors are pieces of paper, and you're drawing a line over them. If the paper is flat, then you're drawing a line of distance n, and the points are n apart. If you fold the ends of the paper together, then the points are 0 units apart (or near enough to make no matter), but that line still has a distance of n.

[Symmetry]

Oh, I think I get what your confusion is now. The signal doesn't have to travel up and over now any more than it did when everything was flat. The signal will travel up a few gate widths to the low resistance metal interconnect layers, travel a few tens or hundreds of gate widths sideways to get to the next transistor, then goes down again to make the connection. Going to 3D doesn't change this except to make the up and down slightly longer and sideways much shorter.

[daeken]

Ah hah, I see what you're saying now. Thanks for clearing that up.

[highfreq]

The previous commenter wasn't talking about this transistor 3d feature, but about stacked transistors. Just like a city full or high-rise buildings can pack a lot more people in per square mile, a stacked transistor IC could pack a lot more transistors per square mm.

[jimmywanger]

The only reason we haven't had stacked transistors now is because of trace density/heat dissipation.

We need pin outs and thermal conductivity - stacking layers of transistors is bad for both.

[highfreq]

He was just referring to packing more transistors in a given area. The theory is that the far transistors of SRAM cache are closer than they would be at a lower density, and that difference might make a performance difference.

I'm not sure what the electrical propagation speed is in modern ICs, but let's assume its about 1mm per pico-second (3 times that of vacuum). So for each mm we move our cache elements closer we gain 2 ps in round-trip delay. On a 3GHz processor you've got 333 ps per cycle, the i5 die is about 13mm across, going from 32 to 22nm process might shave as much as 3 or 4mm of the longest path. Giving a 6 to 8ps gain, potentially a 2% improvement. Interesting.

[gjm11]

> let's assume it's about 1mm per pico-second (3 times that of vacuum).

If Intel had found a way of making signals propagate three times faster than the speed of light in vacuum, everyone would be too busy rewriting the laws of physics to take notice of their transistor technology improvements.

A 3mm path-length difference would be more like 10ps; 20ps for a 2x3mm round trip.

(But I bet Intel take a lot of trouble to reduce those distances. There probably isn't anything that has to happen in a single cycle that involves 6mm-worth of propagation delays.)