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by highfreq
5530 days ago
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He was just referring to packing more transistors in a given area. The theory is that the far transistors of SRAM cache are closer than they would be at a lower density, and that difference might make a performance difference. I'm not sure what the electrical propagation speed is in modern ICs, but let's assume its about 1mm per pico-second (3 times that of vacuum). So for each mm we move our cache elements closer we gain 2 ps in round-trip delay. On a 3GHz processor you've got 333 ps per cycle, the i5 die is about 13mm across, going from 32 to 22nm process might shave as much as 3 or 4mm of the longest path. Giving a 6 to 8ps gain, potentially a 2% improvement. Interesting. |
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If Intel had found a way of making signals propagate three times faster than the speed of light in vacuum, everyone would be too busy rewriting the laws of physics to take notice of their transistor technology improvements.
A 3mm path-length difference would be more like 10ps; 20ps for a 2x3mm round trip.
(But I bet Intel take a lot of trouble to reduce those distances. There probably isn't anything that has to happen in a single cycle that involves 6mm-worth of propagation delays.)