[xvilka]

Hopefully, EDA tools for chip-design will get similar attention too, as well as a "normal" CADs. Software like LibreCAD[1] and FreeCAD[2], Qucs[3], gEDA[4], Yosys[5] and Symbiflow[6], Chisel/FIRRTL[7], OpenROAD initiative[8], Degate[9], and many others.

[1] https://librecad.org/

[2] https://www.freecadweb.org/

[3] https://github.com/Qucs

[4] http://www.geda-project.org/

[5] http://www.clifford.at/yosys/

[6] https://symbiflow.github.io/

[7] https://www.chisel-lang.org/

[8] https://theopenroadproject.org/

[9] https://github.com/nitram2342/degate

[gravypod]

Is there a high level overview, for programmers, of how chip design software works? Something I eventually want to investigate is building some of those pieces of software but I have no idea where to get started learning about that ecosystem. From a software perspective I have a good understanding of how source gets turned into machine code, which gets packaged into shared object code, which then gets linked into a binary. How do those steps work for HDLs? What standards are involved? How do you test that each of those steps works?

[redis_mlc]

The GP mixed up hardware compiler and board layout tools.

KiCad (funded by CERN) and LibreCAD are pretty good PCB layout and routing tools. Since Autodesk bought Eagle, they're the Open Source "great hopes."

For PCB tools, you should just join an existing project since there's several Open Source ones and we need better ones, not more. This is a suitable long-term hobby if you occasionally make boards yourself. Especially welcome if you work on the parts library UI and items.

Chisel, etc. are hardware compiler tools, not board layout tools.

You should get a job at a chip or HFT company and have them pay you to learn and apply this stuff.

The commercial software is shitty since the vendors spend more on keeping their license dongles up-to-date than adding features.

Source: worked at a company that designed a 400 million transistor chip. Most of my X-co-workers worked on the A11 and A12.

[HarryBeadle]

Take a look at Verilog-to-Routing - an educational/research tool that is open-source.

https://github.com/verilog-to-routing/vtr-verilog-to-routing

[gravypod]

That looks like a great resource! Thank you!

[nimish]

Start with an electrical and computer engineering course. Some eda tools are literally fancy vector graphics engines. Some are em simulators wrapped up. Others are circuit modeing tools.

It's not really like programming. The tools are deeply integrated into the physics of the system.

[gravypod]

> It's not really like programming. The tools are deeply integrated into the physics of the system.

What specifically makes electronics different from modeling other systems with software? DSP immediately comes to mind as something that is explicitly tied to Maxwell but there is really good software out there for describing, modeling, and creating signal processing components similar to how you'd write software. An example of this could be GNU Radio.

Is there something that prevents the creation of workflow automation tools, abstractions, and "compilers"/DSLs?

Do engineers at Intel, AMD, and Nvidia manually lay out each feature in their chip designs? If not, what workflow tools have they developed internally? Could those tools, or similar, be used for smaller scale circuit design?

[unlinked_dll]

There’s nothing fundamentally different about modeling electronics. It’s just that modeling nonlinear dynamical systems is a tough nut to crack, be it electronics, weather, heat transfer, whatever. SPICE is pretty good at it, but the newer modeling tools (that dates to the 1970s) are proprietary.

As for the DSLs/workflow/etc there are companies in this space.

[minxomat]

> Do engineers at Intel, AMD, and Nvidia manually lay out each feature in their chip designs? If not, what workflow tools have they developed internally? Could those tools, or similar, be used for smaller scale circuit design?

The answer is yes, but of course not exclusively. There was an English talk at ccc a while ago by an AMD engineer with lots of details on the whole process.

[Taniwha]

Not every feature, typically there will be a physical team that will lay out a gate library, data paths and srams for any particular process - but the bulk of the gates are laid out by CAD tools from high level languages using gates from the gate library

[blcArmadillo]

I haven't personally taken these so can't comment on quality but there is:

1. https://www.coursera.org/learn/vlsi-cad-logic

2. https://www.coursera.org/learn/vlsi-cad-layout

[Cyph0n]

EDA tools are a different beast... There is a reason why the field is completely monopolized by the big three - Cadence, Synopsys, and Mentor Graphics.

And a lot of the tools you mentioned are targeted towards FPGA design rather than full or semi-custom ASIC design. The big three have tools that can handle both.

[paulgerhardt]

Let’s not get ahead of ourselves. Relative to something like Microsoft Office they’re tiny and we have open competitive solutions there (a product notorious for a billion corner cases).

And let’s not forget “EDA software” was single handedly pioneered by one woman and some lisp. Before then, it was hundreds of men taping out circuits on 4x8’ ply with...physical tape who all complained the labor and complexity costs were enormous and nothing could be done.

If we really want to point fingers, we could say it’s a monopoly on the supply chain side of manufacturing - costing millions in NRE’s to make a chip - but if you are willing to scrimp on process size you can get it done for $3 per layer per reticle at 500nm scale and $50 per mask.

[therealcamino]

To make things more concrete than "big" or "relatively...tiny", some quick googling puts Cadence's annual R&D spending at a little less than $1B and Synopsys's around $1.2B. Mentor Graphics is part of Siemens, so that'd be harder to figure out.

[Cyph0n]

It’s a strawman. I never used “big” in an absolute sense, so it’s implied that I meant “big” in their field.

[choudanu4]

Since you seem to know, what company would one go to for fabricating a 500nm chip these days at that price?

[JetSpiegel]

500nm feature size is positively ancient. Any of the myriad fabless companies won't even care about those dinosaur technologies.

I would try the local university with an electronics program.

[Cyph0n]

Are you seriously trying to compare document processors to state of the art EDA tools?