[nimish]

Start with an electrical and computer engineering course. Some eda tools are literally fancy vector graphics engines. Some are em simulators wrapped up. Others are circuit modeing tools.

It's not really like programming. The tools are deeply integrated into the physics of the system.

[gravypod]

> It's not really like programming. The tools are deeply integrated into the physics of the system.

What specifically makes electronics different from modeling other systems with software? DSP immediately comes to mind as something that is explicitly tied to Maxwell but there is really good software out there for describing, modeling, and creating signal processing components similar to how you'd write software. An example of this could be GNU Radio.

Is there something that prevents the creation of workflow automation tools, abstractions, and "compilers"/DSLs?

Do engineers at Intel, AMD, and Nvidia manually lay out each feature in their chip designs? If not, what workflow tools have they developed internally? Could those tools, or similar, be used for smaller scale circuit design?

[unlinked_dll]

There’s nothing fundamentally different about modeling electronics. It’s just that modeling nonlinear dynamical systems is a tough nut to crack, be it electronics, weather, heat transfer, whatever. SPICE is pretty good at it, but the newer modeling tools (that dates to the 1970s) are proprietary.

As for the DSLs/workflow/etc there are companies in this space.

[minxomat]

> Do engineers at Intel, AMD, and Nvidia manually lay out each feature in their chip designs? If not, what workflow tools have they developed internally? Could those tools, or similar, be used for smaller scale circuit design?

The answer is yes, but of course not exclusively. There was an English talk at ccc a while ago by an AMD engineer with lots of details on the whole process.

[Taniwha]

Not every feature, typically there will be a physical team that will lay out a gate library, data paths and srams for any particular process - but the bulk of the gates are laid out by CAD tools from high level languages using gates from the gate library