[minxomat]

> Do engineers at Intel, AMD, and Nvidia manually lay out each feature in their chip designs? If not, what workflow tools have they developed internally? Could those tools, or similar, be used for smaller scale circuit design?

The answer is yes, but of course not exclusively. There was an English talk at ccc a while ago by an AMD engineer with lots of details on the whole process.

[Taniwha]

Not every feature, typically there will be a physical team that will lay out a gate library, data paths and srams for any particular process - but the bulk of the gates are laid out by CAD tools from high level languages using gates from the gate library