[dogber1]

I do not understand the proclaimed 3X increase of design cost per finfet node, particularly in the context of digital ICs. Most cell designs are highly repetitive, so the increased design complexity should only add a one-time offset to the total chip cost. Hence, the total design cost should be comparable to previous nodes, i.e. well below 2X. I understand that purely analog designs are a different beast, but it doesn't make any sense to use advanced nodes for these in the first place (ft/fmax drops as a result of higher-than-linearly scaled CGS).

[kurthr]

Multi-patterned masks are a big expense both in the manufacture, yield, and design/verification. Really, 10nm and below truly need EUV (we used to call it X-ray lithography, but that was already a decade late so they changed the name) to be commercially viable. It brings the mask layers back down to ~60 from 80 @ 10nm... and I assume triple patterning and techniques beyond at 7nm or 5. The mask production and exposure steps balloon without EUV (not using 193nm ArF with crazy NA immersion tricks), but right now the light sources for EUV aren't bright enough to put wafers through at a reasonable speed. https://en.wikipedia.org/wiki/Next-generation_lithography

Also, when you need almost zero defects and the costs of low yields are so big, then a lot (20-30%?) of your budget is spent modeling and confirming your design. Then there is the design of the SOC itself, which only makes sense to do at such geometries, if your level of integration is extreme. Once speed and power stoped scaling with geometry (around 55-28nm), the only reason to keep going was integration and $/transistor, but with higher upfront costs you got more to amortize.

Now don't get me wrong, there's good reason to think that 10nm could be a decent node, and finFETs are cool (low leakage and fast). It's just that I suspect multi-wafer stacking is going to give us a big jump too. We may also leave Si behind. But each of these are really separate jumps rather than incremental.

The problem is that the obvious treadmill is over. The returns are less certain, and once the money men figure that out, there won't be $billions to spend every year. That's the real end to semiconductor age.

[bravo22]

The "design" cost quoted mostly means mask cost. It gets very expensive to produce for smaller nodes.

[adwn]

> The "design" cost quoted mostly means mask cost.

No, mask costs are only a very small part in development and production of complex ASICs. Some sources:

1) First graph in http://electroiq.com/insights-from-leading-edge/2014/02/gate...

2) First graph in http://www.eetimes.com/author.asp?doc_id=1322021

[bravo22]

That's the recurring cost of the mask set, because they don't last forever. The setup cost of the mask however is very high.

As for logic design effort, verilog is verilog. Floor-planning and P&R is a bit more complex at lower nodes but that's mostly software. Also TSMC offers you standard cells to pop into your design.

Therefore most of that "design" cost is in the foundry making the fist set of masks for you, not the incremental mask cost. They're recouping their investment in the process, thus the price is extremely high for newer nodes.

[adwn]

Do you have a source or some links? I would like to know more about this.

[bravo22]

It is mostly based on my experience working as an ASIC designer and having taped out several chips.

However, you can consider it logically -- the engineering effort to design the logic, and perform place and route doesn't change much from node to node. You're doing the same work, with the same software; albeit with new libraries provided by your fab.

The cost clearly correlates with smaller nodes because they charge you a ton to do the "setup" for you, i.e. make the first set of masks. Older nodes are now much cheaper than they were because more shops are using them, thus spreading the amortization costs.

AFAIK, a lot of cortex-M ARM chips (such as STM32F) are made on 90nm nodes. There, the variation you offer your customer is important so they want lower mask costs to make as many variants as possible. The core itself is so small than going to 28nm wouldn't offer much savings because a bulk of the cost is in packaging, testing, and at 28nm would be the amortized mask cost.