[kurthr]

Multi-patterned masks are a big expense both in the manufacture, yield, and design/verification. Really, 10nm and below truly need EUV (we used to call it X-ray lithography, but that was already a decade late so they changed the name) to be commercially viable. It brings the mask layers back down to ~60 from 80 @ 10nm... and I assume triple patterning and techniques beyond at 7nm or 5. The mask production and exposure steps balloon without EUV (not using 193nm ArF with crazy NA immersion tricks), but right now the light sources for EUV aren't bright enough to put wafers through at a reasonable speed. https://en.wikipedia.org/wiki/Next-generation_lithography

Also, when you need almost zero defects and the costs of low yields are so big, then a lot (20-30%?) of your budget is spent modeling and confirming your design. Then there is the design of the SOC itself, which only makes sense to do at such geometries, if your level of integration is extreme. Once speed and power stoped scaling with geometry (around 55-28nm), the only reason to keep going was integration and $/transistor, but with higher upfront costs you got more to amortize.

Now don't get me wrong, there's good reason to think that 10nm could be a decent node, and finFETs are cool (low leakage and fast). It's just that I suspect multi-wafer stacking is going to give us a big jump too. We may also leave Si behind. But each of these are really separate jumps rather than incremental.

The problem is that the obvious treadmill is over. The returns are less certain, and once the money men figure that out, there won't be $billions to spend every year. That's the real end to semiconductor age.