[bravo22]

That's the recurring cost of the mask set, because they don't last forever. The setup cost of the mask however is very high.

As for logic design effort, verilog is verilog. Floor-planning and P&R is a bit more complex at lower nodes but that's mostly software. Also TSMC offers you standard cells to pop into your design.

Therefore most of that "design" cost is in the foundry making the fist set of masks for you, not the incremental mask cost. They're recouping their investment in the process, thus the price is extremely high for newer nodes.

[adwn]

Do you have a source or some links? I would like to know more about this.

[bravo22]

It is mostly based on my experience working as an ASIC designer and having taped out several chips.

However, you can consider it logically -- the engineering effort to design the logic, and perform place and route doesn't change much from node to node. You're doing the same work, with the same software; albeit with new libraries provided by your fab.

The cost clearly correlates with smaller nodes because they charge you a ton to do the "setup" for you, i.e. make the first set of masks. Older nodes are now much cheaper than they were because more shops are using them, thus spreading the amortization costs.

AFAIK, a lot of cortex-M ARM chips (such as STM32F) are made on 90nm nodes. There, the variation you offer your customer is important so they want lower mask costs to make as many variants as possible. The core itself is so small than going to 28nm wouldn't offer much savings because a bulk of the cost is in packaging, testing, and at 28nm would be the amortized mask cost.