[ajross]

Does it do anything different or better than Rocket (or Sodor) that would be notable? Why VHDL instead of the more conventional (heh, for this ISA) Chisel? Would be good to see some notes about architecture in the README just to tell me what I'm looking at.

[inforichland]

I am still leery of the "unconventional" HDLs. I don't really see many of them as much of an improvement over say, VHDL-2008; you get records and functions and instantiation is not as verbose. Yes, the language is a little wordy but it's well proven and I already know it; and many other people know as well, so they can read it and understand it better w/o learning a new language.

[sklogic]

Higher level generator HDLs shine when you want something heavily parametric. VHDL and Verilog code generation features are way too weak, so having a higher level meta-language helps a lot.

[rjsw]

I expect that the author is using VHDL as there is one less translation step involved than when using Chisel.

If Chisel generates HDL which won't synthesize then a typical hardware designer isn't going to get very far trying to debug it.

[_chris_]

Chisel by definition can ONLY generate synthesizable Verilog.

[rjsw]

It wasn't doing for rocket when I tried building it at the weekend and won't even build RISC-V at all right now.

Feel free to fix it.

[gluggymug]

There's two possibilities.

- Rocket has no automated build flow that checks whether committed code is synthesizable.

- you aren't using the same flow as them. I struggled to find what synthesis tools they used just now so I don't blame you!

[rjsw]

The code that is committed isn't directly synthesizable, it needs to be transformed to HDL by a tool that is itself being updated.

I tried what looked to be a supported flow, generate Verilog for FPGAs then synthesize it for Xilinx Zynq devices. The Verilog errors looked correct to me.

[gluggymug]

I saw a little info on that at https://github.com/ucb-bar/fpga-zynq

I guess you are referring to that?

It's supposed to be a relatively mature tool so there's got to be a version that works ok.

[_chris_]

Then please submit an issue to the github issue queue. Don't complain on some internet forum and hope that somebody will read your mind. It works fine for me.

[rjsw]

I don't have a github account.

I just suggested a reason why someone might choose to use a conventional HDL.

[_chris_]

Sure, I don't mean to suggest there aren't valid reasons for writing cores in VHDL, etc., I just want to clarify that Chisel (unlike say Verilog) will, by fiat, only ever generate synthesizable code. If that's ever not the case, you should let them know.