[inforichland]

I am still leery of the "unconventional" HDLs. I don't really see many of them as much of an improvement over say, VHDL-2008; you get records and functions and instantiation is not as verbose. Yes, the language is a little wordy but it's well proven and I already know it; and many other people know as well, so they can read it and understand it better w/o learning a new language.

[sklogic]

Higher level generator HDLs shine when you want something heavily parametric. VHDL and Verilog code generation features are way too weak, so having a higher level meta-language helps a lot.