[gothenburg]

I fail to understand what kind of advantage this language brings to the table compared to the existing solutions.

You touched the subject of the awkward syntax of VHDL. But what about the syntax of Verilog? The syntax seems to be very similar to Verilog.

And besides of the syntax, what are the other features that this language brings that we can't find anywhere else?

And why do you claim that this is oriented "for developers"? Who are these "developers"? Software guys?

[MootWoop]

Don't worry, you're not the first to find that this looks similar to Verilog. I have commented about the syntax aspect on EETimes: see http://www.eetimes.com/author.asp?section_id=36&doc_id=13252...

It's more than the syntax though, it's about having a language for hardware design that most developers (yes software developers) will be able to read, understand, and write. For all sorts of purposes, from playing with FPGAs to designing devices for the IoT. And I think this is something pretty unique :-)

[gothenburg]

What I really wanted was a better explanation of Cx's advantages other than "The syntax is similar to C".

And I'm not sure if you fully understand the difference between a programming language and a hardware description language. Yes, HDL's syntax might be awkward sometimes (whether it's Verilog or VHDL) but I think you are tackling the wrong problems with the wrong way.

Taking the example you gave:

always @(negedge reset_n or posedge clock) begin

  if (~reset_n) begin

    count <= 4'b0;

    FSM <= init;

  end else begin

    case (FSM)

      init: begin

        if (count != 4'h8) begin

          count <= count + 1;

          FSM <= init;

        end else

          FSM <= next_state;

     end

   next_state: // blah

  end
  
 end

end

Can you point exactly what do you think it's wrong with this syntax? And don't compare it with a while() cycle in C, because this is a totally different thing. I'm not saying that this is the perfect way of doing things but there are good reasons why Verilog ended up this way.

I'm really scared with this whole "Hardware design for software developers" thing. Hardware design is very complex and if you aren't careful with what you write, you might end with problems like: CDC, synthesis tools mistaking flip-flops with latches, problems with the insertion of scan chain, and so on.

And by the way, where do you define your clocks in Cx?

[nsiret]

In short, I would say.

(Main) advantages: - The Cx syntax is a lot easier to learn/debug than VHDL and Verilog (and SystemVerilog, and SystemC) - Cx is easier to use for making more complex systems (it's a structured language with Control structures, Subroutines, blocks, etc). - Being easier to use, Cx allows you to write programs faster. Generally these programs are also easier to debug and easier to maintain. Furthermore, it's easier to manage large, complex programs in Cx. - When you do need to have a really low level of abstraction, you can use VHDL/Verilog and call it in Cx

We are here to help people doing better hardware, and to open it to a majority of engineers so I don't think that fully understanding the difference (...) really matters.

Nothing is wrong with the syntax however it's too tedious and complex. In this simple example it's ok but the more larger the FSM the more complexity to handle.

How is this a different thing? The init is the same as a loop (n = 0; n < 5; n++) in software ... It's just more complex to write. I would rather say that you can do the same in C using a switch case statement... but who will code C that way today?

Yes it is complex and error probing, and that is precisely why it is our duty to make it more simple. Handling and preventing the problems is the job of the compiler so hardware makers can focus on what's matter not on these kinds of complexities.

Clocks (and resets) can be either implicit or explicit. By default you only have one clock and reset, and if you need more you can explicit them - http://cx-lang.org/documentation/properties

[correnos]

One difference from Verilog/VHDL is that Cx will handle state machines for procedural code automatically. Bluespec has a similar facility. Also like Bluespec, it makes the clock implicit which makes a lot of code less noisy.

[jclis]

I looked at Bluespec before I tried Cx, it has good points and very powerful features (parameterization of modules comes to mind), but overall I find the semantics to be too complicated for my taste. Rules firing in parallel with custom priorities and possibly non-deterministic?

[correnos]

Bluespec's thing is that rules are atomic, so they won't ever (appear to) fire in parallel. This is in contrast to Verilog and friends where that isn't guaranteed. The nondeterminism comes in when two conflicting rules are both ready to fire: they can't both fire, so the system needs to choose one. You're warned when the compiler detects this, and it can be resolved by giving one a higher priority.

I personally didn't find the semantics to be unreasonably complicated, but the type system is very much based on Haskell's so if you're not used to that there'll be more of a learning curve.