[csirac2]

It's been 10 years since I did much FPGA dev, but at the time I had a lot of fun in Celoxica Handel-C. Sadly I could never quite synthesize my project to the size I could achieve with Verilog. I seem to recall having the Virtex-II datasheets next to me when coding Verliog, not so much with the Handel-C so perhaps I never quite got the hang of driving the language optimally for the target device at hand...

My question is, to a layman like me - does Cx bring something to the table that other C-like HDLs missed?

Edit: I Also very much enjoyed a scheme-like HDL called confluence... Seems it fizzled out. Have any alternative HDLs stuck?

[MootWoop]

I think that the philosophy is different, and this implies a lot of things. We wanted to try something different, create a language and IDE that were easy to use rather than make something more or less compatible with C; and we aimed at making a language that could replace HDLs for most uses in the long term. This is why we created a new language from scratch rather than patching things up on top of C.

In practice, this means saner defaults (and better performance) than past C-like HDLs. Cx is cycle-accurate because this is how digital hardware works, and within a cycle you can have as many instructions as you want. There is no need for Handel-C's "par" statement, and it is much easier to understand and write code with good performance. In Cx, ports (Handel-C channels) can be "bare metal" so you can interact with the rest of the world, or slightly more sophisticated (with an additional synchronization signal). In general Cx is "fat free", what you type is what you get, so I'm pretty confident that logic consumption would remain under control :-) I've never written Handel-C, but from the manual it seems kind of complicated for even the simplest designs, and not very elegant.

I think most alternative HDLs have been abandoned :-/ Often the technology did not meet users' expectations: logic consumption was too high, and it was very difficult to obtain the desired performance. Additionally, I believe that these initiatives weren't targeted at the right public, and the target market itself was way too small. If you're interested, I've written a post about this on our blog: https://blog.synflow.com/marketing-disruptive-innovation/

[csirac2]

Cool! I've actually had a Virtex-6 ML605 eval board for quite some time now, gathering dust... I always wondered what the Synflow toolchain looked like, it seems quite expensive - perhaps I can dust it off for Cx :-)

[nsiret]

You're welcome csirac2. I'm curious to hear about your opinion of our toolchain!

[daphreak]

I don't know if MyHDL(http://www.myhdl.org/) really stuck but I've used it a few times for some smaller things. What I really liked about it was how fast I could simulate while iterating on a design, and the fact that I could use Python unittest for testing.

I will definitely be taking Cx for a spin. Not wasting time with clock/reset/fsm boilerplate will make development faster. If I can get my hands on a trial of their cycle accurate simulator and can automate my test suites I'd be thrilled.

[MootWoop]

Yes it is still in use, and the simulation capabilities are quite advanced! It remains a HDL, better than VHDL and Verilog, so you still have to worry about resetting, clocks and state machine.

Just a word of caution the cycle accurate simulator is still a bit experimental (don't use big numbers, and bit accurate signed arithmetic is not finished yet... we're working on it)

[scott_wilson46]

If you are interested in using python for unit testing there is also Cocotb which is a python based library for running verilog and vhdl simulations. It interfaces to the simulator and allows you to stimulate your design directly from python:

https://github.com/potentialventures/cocotb

[daphreak]

Very interesting. Will definitely look into this.

All of our tests right now are implemented as VHDL/Verilog testbenches. We automate building and running in ISim with a simple Python tool which generates xunit output. It works but its slow and kind of painful to manage testcases.

[davidb_]

Bluespec is a language that's getting attention from academia and industry: http://www.bluespec.com/