[daphreak]

I don't know if MyHDL(http://www.myhdl.org/) really stuck but I've used it a few times for some smaller things. What I really liked about it was how fast I could simulate while iterating on a design, and the fact that I could use Python unittest for testing.

I will definitely be taking Cx for a spin. Not wasting time with clock/reset/fsm boilerplate will make development faster. If I can get my hands on a trial of their cycle accurate simulator and can automate my test suites I'd be thrilled.

[MootWoop]

Yes it is still in use, and the simulation capabilities are quite advanced! It remains a HDL, better than VHDL and Verilog, so you still have to worry about resetting, clocks and state machine.

Just a word of caution the cycle accurate simulator is still a bit experimental (don't use big numbers, and bit accurate signed arithmetic is not finished yet... we're working on it)

[scott_wilson46]

If you are interested in using python for unit testing there is also Cocotb which is a python based library for running verilog and vhdl simulations. It interfaces to the simulator and allows you to stimulate your design directly from python:

https://github.com/potentialventures/cocotb

[daphreak]

Very interesting. Will definitely look into this.

All of our tests right now are implemented as VHDL/Verilog testbenches. We automate building and running in ISim with a simple Python tool which generates xunit output. It works but its slow and kind of painful to manage testcases.