[oxtopus]

FWIW, there is no learning on-chip. Machine learning is not the goal of this project, nor is its success dependent on it's learning capabilities (at least not at this phase). Where it does succeed, however, is in low-power computation in an architecture that is scalable and fault tolerant. LeCunn is criticizing an orange for not tasting like an apple.

[modeless]

Learning may not happen on-chip, but the network is still learned, and the performance of the chip is dependent on the learning. The spiking architecture of the chip means that the best learning algorithms can't be used. An ASIC implementing a convolutional neural net could also be low-power, scalable, and fault-tolerant, while taking advantage of the best currently known learning algorithms and ultimately performing a lot better on real tasks.